v 20110115 2 C 43000 40500 0 0 0 EMBEDDEDtitle-C.sym [ B 43000 40500 22000 17000 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 T 57400 42000 5 10 0 0 0 0 1 graphical=1 L 60900 41100 60900 40500 15 0 0 0 -1 -1 T 57500 40900 15 8 1 0 0 0 1 FILE: T 61000 40900 15 8 1 0 0 0 1 REVISION: T 61000 40600 15 8 1 0 0 0 1 DRAWN BY: T 57500 40600 15 8 1 0 0 0 1 PAGE T 59200 40600 15 8 1 0 0 0 1 OF T 57500 41200 15 8 1 0 0 0 1 TITLE B 57400 40500 7600 1400 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 L 57400 41100 65000 41100 15 0 0 0 -1 -1 ] C 50000 42800 1 0 0 EMBEDDEDcc430f5137.sym [ P 50900 53400 50900 53100 1 0 0 { T 50950 53200 5 8 1 1 0 0 1 pinnumber=27 T 50850 53200 5 8 0 1 0 6 1 pinseq=27 T 50850 52700 9 8 1 1 90 5 1 pinlabel=AVCC_RF T 50900 52900 5 8 0 1 0 5 1 pintype=pwr } P 51300 53400 51300 53100 1 0 0 { T 51350 53200 5 8 1 1 0 0 1 pinnumber=28 T 51250 53200 5 8 0 1 0 6 1 pinseq=28 T 51250 52700 9 8 1 1 90 5 1 pinlabel=AVCC_RF T 51300 52900 5 8 0 1 0 5 1 pintype=pwr } P 51700 53400 51700 53100 1 0 0 { T 51750 53200 5 8 1 1 0 0 1 pinnumber=31 T 51650 53200 5 8 0 1 0 6 1 pinseq=31 T 51650 52700 9 8 1 1 90 5 1 pinlabel=AVCC_RF T 51700 52900 5 8 0 1 0 5 1 pintype=pwr } P 52100 53400 52100 53100 1 0 0 { T 52150 53200 5 8 1 1 0 0 1 pinnumber=32 T 52050 53200 5 8 0 1 0 6 1 pinseq=32 T 52050 52700 9 8 1 1 90 5 1 pinlabel=AVCC_RF T 52100 52900 5 8 0 1 0 5 1 pintype=pwr } P 52500 53400 52500 53100 1 0 0 { T 52550 53200 5 8 1 1 0 0 1 pinnumber=45 T 52450 53200 5 8 0 1 0 6 1 pinseq=45 T 52500 53050 9 8 1 1 0 5 1 pinlabel=AVcc T 52500 52900 5 8 0 1 0 5 1 pintype=pwr } P 52900 53400 52900 53100 1 0 0 { T 52950 53200 5 8 1 1 0 0 1 pinnumber=8 T 52850 53200 5 8 0 1 0 6 1 pinseq=8 T 52900 53050 9 8 1 1 0 5 1 pinlabel=DVcc T 52900 52900 5 8 0 1 0 5 1 pintype=pwr } P 53300 53400 53300 53100 1 0 0 { T 53350 53200 5 8 1 1 0 0 1 pinnumber=22 T 53250 53200 5 8 0 1 0 6 1 pinseq=22 T 53300 53050 9 8 1 1 0 5 1 pinlabel=DVcc T 53300 52900 5 8 0 1 0 5 1 pintype=pwr } P 53700 53400 53700 53100 1 0 0 { T 53750 53200 5 8 1 1 0 0 1 pinnumber=41 T 53650 53200 5 8 0 1 0 6 1 pinseq=41 T 53700 53050 9 8 1 1 0 5 1 pinlabel=DVcc T 53700 52900 5 8 0 1 0 5 1 pintype=pwr } P 54600 52700 54300 52700 1 0 0 { T 54400 52750 5 8 1 1 0 0 1 pinnumber=34 T 54400 52650 5 8 0 1 0 2 1 pinseq=34 T 54250 52700 9 8 1 1 0 6 1 pinlabel=GUARD T 54250 52700 5 8 0 1 0 8 1 pintype=out } P 54600 52300 54300 52300 1 0 0 { T 54400 52350 5 8 1 1 0 0 1 pinnumber=43 T 54400 52250 5 8 0 1 0 2 1 pinseq=43 T 54250 52300 9 8 1 1 0 6 1 pinlabel=(XOUT) P5.1 T 54250 52300 5 8 0 1 0 8 1 pintype=io } P 54600 51900 54300 51900 1 0 0 { T 54400 51950 5 8 1 1 0 0 1 pinnumber=44 T 54400 51850 5 8 0 1 0 2 1 pinseq=44 T 54250 51900 9 8 1 1 0 6 1 pinlabel=(XIN) P5.2 T 54250 51900 5 8 0 1 0 8 1 pintype=io } P 54600 51500 54300 51500 1 0 0 { T 54400 51550 5 8 1 1 0 0 1 pinnumber=35 T 54400 51450 5 8 0 1 0 2 1 pinseq=35 T 54250 51500 9 8 1 1 0 6 1 pinlabel=(TDO) PJ.0 T 54250 51500 5 8 0 1 0 8 1 pintype=io } P 54600 51100 54300 51100 1 0 0 { T 54400 51150 5 8 1 1 0 0 1 pinnumber=36 T 54400 51050 5 8 0 1 0 2 1 pinseq=36 T 54250 51100 9 8 1 1 0 6 1 pinlabel=(TDI/TCLK) PJ.1 T 54250 51100 5 8 0 1 0 8 1 pintype=io } P 54600 50700 54300 50700 1 0 0 { T 54400 50750 5 8 1 1 0 0 1 pinnumber=37 T 54400 50650 5 8 0 1 0 2 1 pinseq=37 T 54250 50700 9 8 1 1 0 6 1 pinlabel=(TMS) PJ.2 T 54250 50700 5 8 0 1 0 8 1 pintype=io } P 54600 50300 54300 50300 1 0 0 { T 54400 50350 5 8 1 1 0 0 1 pinnumber=38 T 54400 50250 5 8 0 1 0 2 1 pinseq=38 T 54250 50300 9 8 1 1 0 6 1 pinlabel=(TCK) PJ.3 T 54250 50300 5 8 0 1 0 8 1 pintype=io } P 54600 49900 54300 49900 1 0 0 { T 54400 49950 5 8 1 1 0 0 1 pinnumber=30 T 54400 49850 5 8 0 1 0 2 1 pinseq=30 T 54250 49900 9 8 1 1 0 6 1 pinlabel=RF_N T 54250 49900 5 8 0 1 0 8 1 pintype=io } P 54600 49500 54300 49500 1 0 0 { T 54400 49550 5 8 1 1 0 0 1 pinnumber=29 T 54400 49450 5 8 0 1 0 2 1 pinseq=29 T 54250 49500 9 8 1 1 0 6 1 pinlabel=RF_P T 54250 49500 5 8 0 1 0 8 1 pintype=io } P 54600 49100 54300 49100 1 0 0 { T 54400 49150 5 8 1 1 0 0 1 pinnumber=25 T 54400 49050 5 8 0 1 0 2 1 pinseq=25 T 54250 49100 9 8 1 1 0 6 1 pinlabel=RF_XIN T 54250 49100 5 8 0 1 0 8 1 pintype=in } P 54600 48700 54300 48700 1 0 0 { T 54400 48750 5 8 1 1 0 0 1 pinnumber=26 T 54400 48650 5 8 0 1 0 2 1 pinseq=26 T 54250 48700 9 8 1 1 0 6 1 pinlabel=RF_XOUT T 54250 48700 5 8 0 1 0 8 1 pintype=out } P 54600 48300 54300 48300 1 0 0 { T 54400 48350 5 8 1 1 0 0 1 pinnumber=40 T 54400 48250 5 8 0 1 0 2 1 pinseq=40 T 54250 48300 9 8 1 1 0 6 1 pinlabel=(NMI/SBWTDIO) \_RST\_ T 54250 48300 5 8 0 1 0 8 1 pintype=io } P 54600 47900 54300 47900 1 0 0 { T 54400 47950 5 8 1 1 0 0 1 pinnumber=33 T 54400 47850 5 8 0 1 0 2 1 pinseq=33 T 54250 47900 9 8 1 1 0 6 1 pinlabel=R_BIAS T 54250 47900 5 8 0 1 0 8 1 pintype=out } P 54600 47500 54300 47500 1 0 0 { T 54400 47550 5 8 1 1 0 0 1 pinnumber=39 T 54400 47450 5 8 0 1 0 2 1 pinseq=39 T 54250 47500 9 8 1 1 0 6 1 pinlabel=(SBWTCK) TEST T 54250 47500 5 8 0 1 0 8 1 pintype=io } P 50000 52700 50300 52700 1 0 0 { T 50200 52750 5 8 1 1 0 6 1 pinnumber=13 T 50200 52650 5 8 0 1 0 8 1 pinseq=13 T 50350 52700 9 8 1 1 0 0 1 pinlabel=P1.0 T 50350 52700 5 8 0 1 0 2 1 pintype=io } P 50000 52300 50300 52300 1 0 0 { T 50200 52350 5 8 1 1 0 6 1 pinnumber=12 T 50200 52250 5 8 0 1 0 8 1 pinseq=12 T 50350 52300 9 8 1 1 0 0 1 pinlabel=P1.1 T 50350 52300 5 8 0 1 0 2 1 pintype=io } P 50000 51900 50300 51900 1 0 0 { T 50200 51950 5 8 1 1 0 6 1 pinnumber=11 T 50200 51850 5 8 0 1 0 8 1 pinseq=11 T 50350 51900 9 8 1 1 0 0 1 pinlabel=P1.2 T 50350 51900 5 8 0 1 0 2 1 pintype=io } P 50000 51500 50300 51500 1 0 0 { T 50200 51550 5 8 1 1 0 6 1 pinnumber=10 T 50200 51450 5 8 0 1 0 8 1 pinseq=10 T 50350 51500 9 8 1 1 0 0 1 pinlabel=P1.3 T 50350 51500 5 8 0 1 0 2 1 pintype=io } P 50000 51100 50300 51100 1 0 0 { T 50200 51150 5 8 1 1 0 6 1 pinnumber=9 T 50200 51050 5 8 0 1 0 8 1 pinseq=9 T 50350 51100 9 8 1 1 0 0 1 pinlabel=P1.4 T 50350 51100 5 8 0 1 0 2 1 pintype=io } P 50000 50700 50300 50700 1 0 0 { T 50200 50750 5 8 1 1 0 6 1 pinnumber=6 T 50200 50650 5 8 0 1 0 8 1 pinseq=6 T 50350 50700 9 8 1 1 0 0 1 pinlabel=P1.5 T 50350 50700 5 8 0 1 0 2 1 pintype=io } P 50000 50300 50300 50300 1 0 0 { T 50200 50350 5 8 1 1 0 6 1 pinnumber=5 T 50200 50250 5 8 0 1 0 8 1 pinseq=5 T 50350 50300 9 8 1 1 0 0 1 pinlabel=P1.6 T 50350 50300 5 8 0 1 0 2 1 pintype=io } P 50000 49900 50300 49900 1 0 0 { T 50200 49950 5 8 1 1 0 6 1 pinnumber=4 T 50200 49850 5 8 0 1 0 8 1 pinseq=4 T 50350 49900 9 8 1 1 0 0 1 pinlabel=P1.7 T 50350 49900 5 8 0 1 0 2 1 pintype=io } P 50000 49500 50300 49500 1 0 0 { T 50200 49550 5 8 1 1 0 6 1 pinnumber=3 T 50200 49450 5 8 0 1 0 8 1 pinseq=3 T 50350 49500 9 8 1 1 0 0 1 pinlabel=P2.0 (A0) T 50350 49500 5 8 0 1 0 2 1 pintype=io } P 50000 49100 50300 49100 1 0 0 { T 50200 49150 5 8 1 1 0 6 1 pinnumber=2 T 50200 49050 5 8 0 1 0 8 1 pinseq=2 T 50350 49100 9 8 1 1 0 0 1 pinlabel=P2.1 (A1) T 50350 49100 5 8 0 1 0 2 1 pintype=io } P 50000 48700 50300 48700 1 0 0 { T 50200 48750 5 8 1 1 0 6 1 pinnumber=1 T 50200 48650 5 8 0 1 0 8 1 pinseq=1 T 50350 48700 9 8 1 1 0 0 1 pinlabel=P2.2 (A2) T 50350 48700 5 8 0 1 0 2 1 pintype=io } P 50000 48300 50300 48300 1 0 0 { T 50200 48350 5 8 1 1 0 6 1 pinnumber=48 T 50200 48250 5 8 0 1 0 8 1 pinseq=48 T 50350 48300 9 8 1 1 0 0 1 pinlabel=P2.3in T 50350 48300 5 8 0 1 0 2 1 pintype=io } P 50000 47900 50300 47900 1 0 0 { T 50200 47950 5 8 1 1 0 6 1 pinnumber=47 T 50200 47850 5 8 0 1 0 8 1 pinseq=47 T 50350 47900 9 8 1 1 0 0 1 pinlabel=P2.4 T 50350 47900 5 8 0 1 0 2 1 pintype=io } P 50000 47500 50300 47500 1 0 0 { T 50200 47550 5 8 1 1 0 6 1 pinnumber=46 T 50200 47450 5 8 0 1 0 8 1 pinseq=46 T 50350 47500 9 8 1 1 0 0 1 pinlabel=P2.5 T 50350 47500 5 8 0 1 0 2 1 pintype=io } P 50000 47100 50300 47100 1 0 0 { T 50200 47150 5 8 1 1 0 6 1 pinnumber=24 T 50200 47050 5 8 0 1 0 8 1 pinseq=24 T 50350 47100 9 8 1 1 0 0 1 pinlabel=P2.6 T 50350 47100 5 8 0 1 0 2 1 pintype=io } P 50000 46700 50300 46700 1 0 0 { T 50200 46750 5 8 1 1 0 6 1 pinnumber=23 T 50200 46650 5 8 0 1 0 8 1 pinseq=23 T 50350 46700 9 8 1 1 0 0 1 pinlabel=P2.7 T 50350 46700 5 8 0 1 0 2 1 pintype=io } P 50000 46300 50300 46300 1 0 0 { T 50200 46350 5 8 1 1 0 6 1 pinnumber=21 T 50200 46250 5 8 0 1 0 8 1 pinseq=21 T 50350 46300 9 8 1 1 0 0 1 pinlabel=P3.0 T 50350 46300 5 8 0 1 0 2 1 pintype=io } P 50000 45900 50300 45900 1 0 0 { T 50200 45950 5 8 1 1 0 6 1 pinnumber=20 T 50200 45850 5 8 0 1 0 8 1 pinseq=20 T 50350 45900 9 8 1 1 0 0 1 pinlabel=P3.1 T 50350 45900 5 8 0 1 0 2 1 pintype=io } P 50000 45500 50300 45500 1 0 0 { T 50200 45550 5 8 1 1 0 6 1 pinnumber=19 T 50200 45450 5 8 0 1 0 8 1 pinseq=19 T 50350 45500 9 8 1 1 0 0 1 pinlabel=P3.2 T 50350 45500 5 8 0 1 0 2 1 pintype=io } P 50000 45100 50300 45100 1 0 0 { T 50200 45150 5 8 1 1 0 6 1 pinnumber=18 T 50200 45050 5 8 0 1 0 8 1 pinseq=18 T 50350 45100 9 8 1 1 0 0 1 pinlabel=P3.3 T 50350 45100 5 8 0 1 0 2 1 pintype=io } P 50000 44700 50300 44700 1 0 0 { T 50200 44750 5 8 1 1 0 6 1 pinnumber=17 T 50200 44650 5 8 0 1 0 8 1 pinseq=17 T 50350 44700 9 8 1 1 0 0 1 pinlabel=P3.4 T 50350 44700 5 8 0 1 0 2 1 pintype=io } P 50000 44300 50300 44300 1 0 0 { T 50200 44350 5 8 1 1 0 6 1 pinnumber=16 T 50200 44250 5 8 0 1 0 8 1 pinseq=16 T 50350 44300 9 8 1 1 0 0 1 pinlabel=P3.5 T 50350 44300 5 8 0 1 0 2 1 pintype=io } P 50000 43900 50300 43900 1 0 0 { T 50200 43950 5 8 1 1 0 6 1 pinnumber=15 T 50200 43850 5 8 0 1 0 8 1 pinseq=15 T 50350 43900 9 8 1 1 0 0 1 pinlabel=P3.6 T 50350 43900 5 8 0 1 0 2 1 pintype=io } P 50000 43500 50300 43500 1 0 0 { T 50200 43550 5 8 1 1 0 6 1 pinnumber=14 T 50200 43450 5 8 0 1 0 8 1 pinseq=14 T 50350 43500 9 8 1 1 0 0 1 pinlabel=P3.7 T 50350 43500 5 8 0 1 0 2 1 pintype=io } P 51900 42800 51900 43100 1 0 0 { T 51950 43000 5 8 1 1 0 2 1 pinnumber=42 T 51850 43000 5 8 0 1 0 8 1 pinseq=42 T 51900 43150 9 8 1 1 0 3 1 pinlabel=AVss T 51900 43300 5 8 0 1 0 3 1 pintype=pwr } P 52300 42800 52300 43100 1 0 0 { T 52350 43000 5 8 1 1 0 2 1 pinnumber=7 T 52250 43000 5 8 0 1 0 8 1 pinseq=7 T 52300 43150 9 8 1 1 0 3 1 pinlabel=Vcore T 52300 43300 5 8 0 1 0 3 1 pintype=out } P 52700 42800 52700 43100 1 0 0 { T 52750 43000 5 8 1 1 0 2 1 pinnumber=49 T 52650 43000 5 8 0 1 0 8 1 pinseq=49 T 52700 43150 9 8 1 1 0 3 1 pinlabel=Vss T 52700 43300 5 8 0 1 0 3 1 pintype=pwr } B 50300 43100 4000 10000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 T 54300 53200 8 10 0 1 0 6 1 refdes=U? T 52100 48000 9 10 1 0 0 0 1 CC430F5137 T 52100 48300 5 10 0 0 0 0 1 device=CC430F5137 T 52100 48500 5 10 0 0 0 0 1 footprint=QFN48_7_EP T 52100 48700 5 10 0 0 0 0 1 author=Andrew H. Armenia T 52100 48900 5 10 0 0 0 0 1 documentation=Texas Instruments datasheet T 52100 49100 5 10 0 0 0 0 1 description=MSP430 RF System-On-Chip T 52100 49300 5 10 0 0 0 0 1 numslots=0 T 52100 49500 5 10 0 0 0 0 1 dist-license=BSD T 52100 49700 5 10 0 0 0 0 1 use-license=BSD ] { T 54300 53200 5 10 1 1 0 6 1 refdes=U100 T 52100 48300 5 10 0 0 0 0 1 device=CC430F5137 T 52100 48500 5 10 0 0 0 0 1 footprint=QFN48_7_EP } N 50900 53400 50900 54000 4 N 50900 54000 54900 54000 4 N 54900 54000 54900 52700 4 N 54900 52700 54600 52700 4 N 51300 53400 51300 54000 4 N 51700 53400 51700 54000 4 N 52100 53400 52100 54000 4 N 52900 53400 52900 54000 4 N 53700 54000 53700 53400 4 N 53300 53400 53300 54000 4 N 51900 41600 51900 42800 4 N 52700 42800 52700 41600 4 C 59800 48700 1 0 0 EMBEDDED0896BM15A0001.sym [ P 62000 49900 61700 49900 1 0 0 { T 61800 49950 5 8 1 1 0 0 1 pinnumber=1 T 61800 49850 5 8 0 1 0 2 1 pinseq=1 T 61650 49900 9 8 1 1 0 6 1 pinlabel=UNBAL T 61650 49900 5 8 0 1 0 8 1 pintype=io } P 59900 49500 60200 49500 1 0 0 { T 60100 49550 5 8 1 1 0 6 1 pinnumber=4 T 60100 49450 5 8 0 1 0 8 1 pinseq=4 T 60250 49500 9 8 1 1 0 0 1 pinlabel=BAL_N T 60250 49500 5 8 0 1 0 2 1 pintype=io } P 59900 49900 60200 49900 1 0 0 { T 60100 49950 5 8 1 1 0 6 1 pinnumber=3 T 60100 49850 5 8 0 1 0 8 1 pinseq=3 T 60250 49900 9 8 1 1 0 0 1 pinlabel=BAL_P T 60250 49900 5 8 0 1 0 2 1 pintype=io } P 60600 48800 60600 49100 1 0 0 { T 60650 49000 5 8 1 1 0 2 1 pinnumber=2 T 60550 49000 5 8 0 1 0 8 1 pinseq=2 T 60600 49150 9 8 1 1 0 3 1 pinlabel=GND T 60600 49300 5 8 0 1 0 3 1 pintype=io } P 61000 48800 61000 49100 1 0 0 { T 61050 49000 5 8 1 1 0 2 1 pinnumber=5 T 60950 49000 5 8 0 1 0 8 1 pinseq=5 T 61000 49150 9 8 1 1 0 3 1 pinlabel=GND T 61000 49300 5 8 0 1 0 3 1 pintype=io } P 61400 48800 61400 49100 1 0 0 { T 61450 49000 5 8 1 1 0 2 1 pinnumber=6 T 61350 49000 5 8 0 1 0 8 1 pinseq=6 T 61400 49150 9 8 1 1 0 3 1 pinlabel=GND T 61400 49300 5 8 0 1 0 3 1 pintype=io } B 60200 49100 1500 1200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 T 61700 50400 8 10 0 1 0 6 1 refdes=T? T 60200 50400 9 10 1 0 0 0 1 0896BM15A0001 T 60200 50600 5 10 0 0 0 0 1 device=0896BM15A0001 T 60200 50800 5 10 0 0 0 0 1 footprint=0896BM15A0001 T 60200 51000 5 10 0 0 0 0 1 author=Andrew H. Armenia T 60200 51200 5 10 0 0 0 0 1 documentation=Johanson Technology datasheet T 60200 51400 5 10 0 0 0 0 1 description=RF Balun for TI CC1101 Radio T 60200 51600 5 10 0 0 0 0 1 numslots=0 T 60200 51800 5 10 0 0 0 0 1 dist-license=BSD T 60200 52000 5 10 0 0 0 0 1 use-license=BSD ] { T 60400 50600 5 10 1 1 0 6 1 refdes=T100 T 60200 50600 5 10 0 0 0 0 1 device=0433BM15A0001E T 60200 50800 5 10 0 0 0 0 1 footprint=0896BM15A0001 } N 54600 49900 59900 49900 4 N 54600 49500 59900 49500 4 N 61000 48300 61000 48800 4 N 61400 48500 61400 48800 4 N 61000 48500 60600 48500 4 N 60600 48500 60600 48800 4 T 56900 49500 9 10 1 0 0 0 2 Minimize length of balanced transmission line C 58300 49200 1 180 0 EMBEDDEDcrystal-1.sym [ P 58300 49100 58100 49100 1 0 0 { T 58150 49050 5 8 0 1 180 6 1 pinnumber=1 T 58150 49150 5 8 0 1 180 8 1 pinseq=1 T 58050 49100 9 8 0 1 180 0 1 pinlabel=1 T 58050 49100 5 8 0 1 180 2 1 pintype=pas } P 57800 49100 57600 49100 1 0 1 { T 57750 49050 5 8 0 1 180 0 1 pinnumber=2 T 57750 49150 5 8 0 1 180 2 1 pinseq=2 T 57850 49100 9 8 0 1 180 6 1 pinlabel=2 T 57850 49100 5 8 0 1 180 8 1 pintype=pas } B 57850 49000 200 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 T 58100 48700 5 10 0 0 180 0 1 device=CRYSTAL L 58100 48960 58100 49240 3 0 0 0 -1 -1 L 57800 48960 57800 49240 3 0 0 0 -1 -1 T 58100 48900 8 10 0 1 180 0 1 refdes=U? T 58100 48100 5 10 0 0 180 0 1 description=crystal T 58100 48300 5 10 0 0 180 0 1 numslots=0 T 58100 48500 5 10 0 0 180 0 1 symversion=0.1 ] { T 58100 48700 5 10 0 0 180 0 1 device=CRYSTAL T 58100 48900 5 10 1 1 180 0 1 refdes=X101 T 58300 49200 5 10 0 1 0 0 1 footprint=NX3225SA T 58300 49200 5 10 1 1 0 0 1 value=26.000MHz T 58300 49200 5 10 0 0 0 0 1 netname=0.1 } N 57600 49100 54600 49100 4 N 58300 49100 58500 49100 4 N 58500 48500 58500 49100 4 N 58500 48700 54600 48700 4 C 58700 47600 1 90 0 EMBEDDEDcapacitor-1.sym [ P 58500 47600 58500 47800 1 0 0 { T 58450 47750 5 8 0 1 90 6 1 pinnumber=1 T 58550 47750 5 8 0 1 90 8 1 pinseq=1 T 58500 47800 9 8 0 1 90 0 1 pinlabel=1 T 58500 47800 5 8 0 1 90 2 1 pintype=pas } P 58500 48500 58500 48300 1 0 0 { T 58450 48350 5 8 0 1 90 0 1 pinnumber=2 T 58550 48350 5 8 0 1 90 2 1 pinseq=2 T 58500 48300 9 8 0 1 90 6 1 pinlabel=2 T 58500 48300 5 8 0 1 90 8 1 pintype=pas } L 58300 48000 58700 48000 3 0 0 0 -1 -1 L 58300 48100 58700 48100 3 0 0 0 -1 -1 L 58500 48300 58500 48100 3 0 0 0 -1 -1 L 58500 48000 58500 47800 3 0 0 0 -1 -1 T 58000 47800 5 10 0 0 90 0 1 device=CAPACITOR T 58200 47800 8 10 0 1 90 0 1 refdes=C? T 57400 47800 5 10 0 0 90 0 1 description=capacitor T 57600 47800 5 10 0 0 90 0 1 numslots=0 T 57800 47800 5 10 0 0 90 0 1 symversion=0.1 ] { T 58000 47800 5 10 0 0 90 0 1 device=CAPACITOR T 58200 47800 5 10 1 1 90 0 1 refdes=C102 T 58700 47600 5 10 0 1 0 0 1 footprint=0402 T 58700 47500 5 10 1 1 90 0 1 value=10pF } C 57700 47600 1 90 0 EMBEDDEDcapacitor-1.sym [ P 57500 47600 57500 47800 1 0 0 { T 57450 47750 5 8 0 1 90 6 1 pinnumber=1 T 57550 47750 5 8 0 1 90 8 1 pinseq=1 T 57500 47800 9 8 0 1 90 0 1 pinlabel=1 T 57500 47800 5 8 0 1 90 2 1 pintype=pas } P 57500 48500 57500 48300 1 0 0 { T 57450 48350 5 8 0 1 90 0 1 pinnumber=2 T 57550 48350 5 8 0 1 90 2 1 pinseq=2 T 57500 48300 9 8 0 1 90 6 1 pinlabel=2 T 57500 48300 5 8 0 1 90 8 1 pintype=pas } L 57300 48000 57700 48000 3 0 0 0 -1 -1 L 57300 48100 57700 48100 3 0 0 0 -1 -1 L 57500 48300 57500 48100 3 0 0 0 -1 -1 L 57500 48000 57500 47800 3 0 0 0 -1 -1 T 57000 47800 5 10 0 0 90 0 1 device=CAPACITOR T 57200 47800 8 10 0 1 90 0 1 refdes=C? T 56400 47800 5 10 0 0 90 0 1 description=capacitor T 56600 47800 5 10 0 0 90 0 1 numslots=0 T 56800 47800 5 10 0 0 90 0 1 symversion=0.1 ] { T 57000 47800 5 10 0 0 90 0 1 device=CAPACITOR T 57200 47800 5 10 1 1 90 0 1 refdes=C100 T 57700 47600 5 10 0 1 0 0 1 footprint=0402 T 57900 47500 5 10 1 1 90 0 1 value=10pF } N 57500 48500 57500 49100 4 N 58000 47400 58000 47500 4 N 57500 47500 58500 47500 4 N 58500 47500 58500 47600 4 N 57500 47500 57500 47600 4 C 56800 46000 1 90 0 EMBEDDEDresistor-1.sym [ L 56600 46600 56800 46500 3 0 0 0 -1 -1 L 56800 46500 56600 46400 3 0 0 0 -1 -1 L 56600 46400 56800 46300 3 0 0 0 -1 -1 L 56800 46300 56600 46200 3 0 0 0 -1 -1 T 56400 46300 5 10 0 0 90 0 1 device=RESISTOR L 56600 46600 56800 46700 3 0 0 0 -1 -1 L 56800 46700 56700 46750 3 0 0 0 -1 -1 P 56700 46900 56700 46750 1 0 0 { T 56650 46800 5 8 0 1 90 0 1 pinnumber=2 T 56650 46800 5 8 0 0 90 0 1 pinseq=2 T 56650 46800 5 8 0 1 90 0 1 pinlabel=2 T 56650 46800 5 8 0 1 90 0 1 pintype=pas } P 56700 46000 56700 46152 1 0 0 { T 56650 46100 5 8 0 1 90 0 1 pinnumber=1 T 56650 46100 5 8 0 0 90 0 1 pinseq=1 T 56650 46100 5 8 0 1 90 0 1 pinlabel=1 T 56650 46100 5 8 0 1 90 0 1 pintype=pas } L 56600 46201 56700 46150 3 0 0 0 -1 -1 T 56500 46200 8 10 0 1 90 0 1 refdes=R? T 56800 46000 8 10 0 1 90 0 1 pins=2 T 56800 46000 8 10 0 1 90 0 1 class=DISCRETE ] { T 56400 46300 5 10 0 0 90 0 1 device=RESISTOR T 56500 46200 5 10 1 1 90 0 1 refdes=R101 T 56800 46000 5 10 0 1 0 0 1 footprint=0402 T 57000 46100 5 10 1 1 90 0 1 value=56k 1% } N 54600 47900 56700 47900 4 N 56700 47900 56700 46900 4 N 56700 45900 56700 46000 4 N 55600 48300 55600 44900 4 N 55600 44900 57400 44900 4 C 57500 45100 1 90 0 EMBEDDEDresistor-1.sym [ L 57300 45700 57500 45600 3 0 0 0 -1 -1 L 57500 45600 57300 45500 3 0 0 0 -1 -1 L 57300 45500 57500 45400 3 0 0 0 -1 -1 L 57500 45400 57300 45300 3 0 0 0 -1 -1 T 57100 45400 5 10 0 0 90 0 1 device=RESISTOR L 57300 45700 57500 45800 3 0 0 0 -1 -1 L 57500 45800 57400 45850 3 0 0 0 -1 -1 P 57400 46000 57400 45850 1 0 0 { T 57350 45900 5 8 0 1 90 0 1 pinnumber=2 T 57350 45900 5 8 0 0 90 0 1 pinseq=2 T 57350 45900 5 8 0 1 90 0 1 pinlabel=2 T 57350 45900 5 8 0 1 90 0 1 pintype=pas } P 57400 45100 57400 45252 1 0 0 { T 57350 45200 5 8 0 1 90 0 1 pinnumber=1 T 57350 45200 5 8 0 0 90 0 1 pinseq=1 T 57350 45200 5 8 0 1 90 0 1 pinlabel=1 T 57350 45200 5 8 0 1 90 0 1 pintype=pas } L 57300 45301 57400 45250 3 0 0 0 -1 -1 T 57200 45300 8 10 0 1 90 0 1 refdes=R? T 57500 45100 8 10 0 1 90 0 1 pins=2 T 57500 45100 8 10 0 1 90 0 1 class=DISCRETE ] { T 57100 45400 5 10 0 0 90 0 1 device=RESISTOR T 57200 45300 5 10 1 1 90 0 1 refdes=R102 T 57500 45100 5 10 0 1 0 0 1 footprint=0402 T 57700 45300 5 10 1 1 90 0 1 value=100k } C 57200 46100 1 0 0 EMBEDDEDgeneric-power.sym [ P 57400 46100 57400 46300 1 0 0 { T 57450 46150 5 6 0 1 0 0 1 pinnumber=1 T 57450 46150 5 6 0 0 0 0 1 pinseq=1 T 57450 46150 5 6 0 1 0 0 1 pinlabel=1 T 57450 46150 5 6 0 1 0 0 1 pintype=pwr } L 57250 46300 57550 46300 3 0 0 0 -1 -1 T 57400 46350 8 10 0 1 0 3 1 net=Vcc:1 ] { T 57400 46350 5 10 1 1 0 3 1 net=VCC33:1 } N 57400 46000 57400 46100 4 N 45800 49100 46000 49100 4 N 46000 48900 46000 49100 4 C 52100 54200 1 0 0 EMBEDDEDgeneric-power.sym [ P 52300 54200 52300 54400 1 0 0 { T 52350 54250 5 6 0 1 0 0 1 pinnumber=1 T 52350 54250 5 6 0 0 0 0 1 pinseq=1 T 52350 54250 5 6 0 1 0 0 1 pinlabel=1 T 52350 54250 5 6 0 1 0 0 1 pintype=pwr } L 52150 54400 52450 54400 3 0 0 0 -1 -1 T 52300 54450 8 10 0 1 0 3 1 net=Vcc:1 ] { T 52300 54450 5 10 1 1 0 3 1 net=VCC33:1 } C 61400 56200 1 0 0 EMBEDDEDgeneric-power.sym [ P 61600 56200 61600 56400 1 0 0 { T 61650 56250 5 6 0 1 0 0 1 pinnumber=1 T 61650 56250 5 6 0 0 0 0 1 pinseq=1 T 61650 56250 5 6 0 1 0 0 1 pinlabel=1 T 61650 56250 5 6 0 1 0 0 1 pintype=pwr } L 61450 56400 61750 56400 3 0 0 0 -1 -1 T 61600 56450 8 10 0 1 0 3 1 net=Vcc:1 ] { T 61600 56450 5 10 1 1 0 3 1 net=VCC33:1 } C 55400 55100 1 90 0 EMBEDDEDcapacitor-1.sym [ P 55200 55100 55200 55300 1 0 0 { T 55150 55250 5 8 0 1 90 6 1 pinnumber=1 T 55250 55250 5 8 0 1 90 8 1 pinseq=1 T 55200 55300 9 8 0 1 90 0 1 pinlabel=1 T 55200 55300 5 8 0 1 90 2 1 pintype=pas } P 55200 56000 55200 55800 1 0 0 { T 55150 55850 5 8 0 1 90 0 1 pinnumber=2 T 55250 55850 5 8 0 1 90 2 1 pinseq=2 T 55200 55800 9 8 0 1 90 6 1 pinlabel=2 T 55200 55800 5 8 0 1 90 8 1 pintype=pas } L 55000 55500 55400 55500 3 0 0 0 -1 -1 L 55000 55600 55400 55600 3 0 0 0 -1 -1 L 55200 55800 55200 55600 3 0 0 0 -1 -1 L 55200 55500 55200 55300 3 0 0 0 -1 -1 T 54700 55300 5 10 0 0 90 0 1 device=CAPACITOR T 54900 55300 8 10 0 1 90 0 1 refdes=C? T 54100 55300 5 10 0 0 90 0 1 description=capacitor T 54300 55300 5 10 0 0 90 0 1 numslots=0 T 54500 55300 5 10 0 0 90 0 1 symversion=0.1 ] { T 54700 55300 5 10 0 0 90 0 1 device=CAPACITOR T 54900 55300 5 10 1 1 90 0 1 refdes=CD1001 T 55400 55100 5 10 0 1 0 0 1 footprint=0402 T 55400 55000 5 10 1 1 90 0 1 value=0.1uF } C 56200 55100 1 90 0 EMBEDDEDcapacitor-1.sym [ P 56000 55100 56000 55300 1 0 0 { T 55950 55250 5 8 0 1 90 6 1 pinnumber=1 T 56050 55250 5 8 0 1 90 8 1 pinseq=1 T 56000 55300 9 8 0 1 90 0 1 pinlabel=1 T 56000 55300 5 8 0 1 90 2 1 pintype=pas } P 56000 56000 56000 55800 1 0 0 { T 55950 55850 5 8 0 1 90 0 1 pinnumber=2 T 56050 55850 5 8 0 1 90 2 1 pinseq=2 T 56000 55800 9 8 0 1 90 6 1 pinlabel=2 T 56000 55800 5 8 0 1 90 8 1 pintype=pas } L 55800 55500 56200 55500 3 0 0 0 -1 -1 L 55800 55600 56200 55600 3 0 0 0 -1 -1 L 56000 55800 56000 55600 3 0 0 0 -1 -1 L 56000 55500 56000 55300 3 0 0 0 -1 -1 T 55500 55300 5 10 0 0 90 0 1 device=CAPACITOR T 55700 55300 8 10 0 1 90 0 1 refdes=C? T 54900 55300 5 10 0 0 90 0 1 description=capacitor T 55100 55300 5 10 0 0 90 0 1 numslots=0 T 55300 55300 5 10 0 0 90 0 1 symversion=0.1 ] { T 55500 55300 5 10 0 0 90 0 1 device=CAPACITOR T 55800 55300 5 10 1 1 90 0 1 refdes=CD1002 T 56200 55100 5 10 0 1 0 0 1 footprint=0402 T 56200 55000 5 10 1 1 90 0 1 value=0.1uF } C 57000 55100 1 90 0 EMBEDDEDcapacitor-1.sym [ P 56800 55100 56800 55300 1 0 0 { T 56750 55250 5 8 0 1 90 6 1 pinnumber=1 T 56850 55250 5 8 0 1 90 8 1 pinseq=1 T 56800 55300 9 8 0 1 90 0 1 pinlabel=1 T 56800 55300 5 8 0 1 90 2 1 pintype=pas } P 56800 56000 56800 55800 1 0 0 { T 56750 55850 5 8 0 1 90 0 1 pinnumber=2 T 56850 55850 5 8 0 1 90 2 1 pinseq=2 T 56800 55800 9 8 0 1 90 6 1 pinlabel=2 T 56800 55800 5 8 0 1 90 8 1 pintype=pas } L 56600 55500 57000 55500 3 0 0 0 -1 -1 L 56600 55600 57000 55600 3 0 0 0 -1 -1 L 56800 55800 56800 55600 3 0 0 0 -1 -1 L 56800 55500 56800 55300 3 0 0 0 -1 -1 T 56300 55300 5 10 0 0 90 0 1 device=CAPACITOR T 56500 55300 8 10 0 1 90 0 1 refdes=C? T 55700 55300 5 10 0 0 90 0 1 description=capacitor T 55900 55300 5 10 0 0 90 0 1 numslots=0 T 56100 55300 5 10 0 0 90 0 1 symversion=0.1 ] { T 56300 55300 5 10 0 0 90 0 1 device=CAPACITOR T 56600 55300 5 10 1 1 90 0 1 refdes=CD1003 T 57000 55100 5 10 0 1 0 0 1 footprint=0402 T 57000 55000 5 10 1 1 90 0 1 value=0.1uF } C 57900 55100 1 90 0 EMBEDDEDcapacitor-1.sym [ P 57700 55100 57700 55300 1 0 0 { T 57650 55250 5 8 0 1 90 6 1 pinnumber=1 T 57750 55250 5 8 0 1 90 8 1 pinseq=1 T 57700 55300 9 8 0 1 90 0 1 pinlabel=1 T 57700 55300 5 8 0 1 90 2 1 pintype=pas } P 57700 56000 57700 55800 1 0 0 { T 57650 55850 5 8 0 1 90 0 1 pinnumber=2 T 57750 55850 5 8 0 1 90 2 1 pinseq=2 T 57700 55800 9 8 0 1 90 6 1 pinlabel=2 T 57700 55800 5 8 0 1 90 8 1 pintype=pas } L 57500 55500 57900 55500 3 0 0 0 -1 -1 L 57500 55600 57900 55600 3 0 0 0 -1 -1 L 57700 55800 57700 55600 3 0 0 0 -1 -1 L 57700 55500 57700 55300 3 0 0 0 -1 -1 T 57200 55300 5 10 0 0 90 0 1 device=CAPACITOR T 57400 55300 8 10 0 1 90 0 1 refdes=C? T 56600 55300 5 10 0 0 90 0 1 description=capacitor T 56800 55300 5 10 0 0 90 0 1 numslots=0 T 57000 55300 5 10 0 0 90 0 1 symversion=0.1 ] { T 57200 55300 5 10 0 0 90 0 1 device=CAPACITOR T 57500 55300 5 10 1 1 90 0 1 refdes=C107 T 57900 55100 5 10 0 1 0 0 1 footprint=0603 T 57900 55000 5 10 1 1 90 0 1 value=10uF } N 55200 55100 55200 55000 4 N 55200 55000 57700 55000 4 N 57700 56100 55200 56100 4 N 55200 56100 55200 56000 4 N 56800 56200 56800 56100 4 N 57700 56000 57700 56100 4 N 57700 55100 57700 55000 4 N 56800 55100 56800 55000 4 N 56000 55100 56000 55000 4 N 56000 56000 56000 56100 4 N 56800 56000 56800 56100 4 C 60600 55100 1 90 0 EMBEDDEDcapacitor-1.sym [ P 60400 55100 60400 55300 1 0 0 { T 60350 55250 5 8 0 1 90 6 1 pinnumber=1 T 60450 55250 5 8 0 1 90 8 1 pinseq=1 T 60400 55300 9 8 0 1 90 0 1 pinlabel=1 T 60400 55300 5 8 0 1 90 2 1 pintype=pas } P 60400 56000 60400 55800 1 0 0 { T 60350 55850 5 8 0 1 90 0 1 pinnumber=2 T 60450 55850 5 8 0 1 90 2 1 pinseq=2 T 60400 55800 9 8 0 1 90 6 1 pinlabel=2 T 60400 55800 5 8 0 1 90 8 1 pintype=pas } L 60200 55500 60600 55500 3 0 0 0 -1 -1 L 60200 55600 60600 55600 3 0 0 0 -1 -1 L 60400 55800 60400 55600 3 0 0 0 -1 -1 L 60400 55500 60400 55300 3 0 0 0 -1 -1 T 59900 55300 5 10 0 0 90 0 1 device=CAPACITOR T 60100 55300 8 10 0 1 90 0 1 refdes=C? T 59300 55300 5 10 0 0 90 0 1 description=capacitor T 59500 55300 5 10 0 0 90 0 1 numslots=0 T 59700 55300 5 10 0 0 90 0 1 symversion=0.1 ] { T 59900 55300 5 10 0 0 90 0 1 device=CAPACITOR T 60200 55300 5 10 1 1 90 0 1 refdes=CD1005 T 60600 55100 5 10 0 1 0 0 1 footprint=0402 T 60600 55000 5 10 1 1 90 0 1 value=0.1uF } C 61400 55100 1 90 0 EMBEDDEDcapacitor-1.sym [ P 61200 55100 61200 55300 1 0 0 { T 61150 55250 5 8 0 1 90 6 1 pinnumber=1 T 61250 55250 5 8 0 1 90 8 1 pinseq=1 T 61200 55300 9 8 0 1 90 0 1 pinlabel=1 T 61200 55300 5 8 0 1 90 2 1 pintype=pas } P 61200 56000 61200 55800 1 0 0 { T 61150 55850 5 8 0 1 90 0 1 pinnumber=2 T 61250 55850 5 8 0 1 90 2 1 pinseq=2 T 61200 55800 9 8 0 1 90 6 1 pinlabel=2 T 61200 55800 5 8 0 1 90 8 1 pintype=pas } L 61000 55500 61400 55500 3 0 0 0 -1 -1 L 61000 55600 61400 55600 3 0 0 0 -1 -1 L 61200 55800 61200 55600 3 0 0 0 -1 -1 L 61200 55500 61200 55300 3 0 0 0 -1 -1 T 60700 55300 5 10 0 0 90 0 1 device=CAPACITOR T 60900 55300 8 10 0 1 90 0 1 refdes=C? T 60100 55300 5 10 0 0 90 0 1 description=capacitor T 60300 55300 5 10 0 0 90 0 1 numslots=0 T 60500 55300 5 10 0 0 90 0 1 symversion=0.1 ] { T 60700 55300 5 10 0 0 90 0 1 device=CAPACITOR T 60900 55300 5 10 1 1 90 0 1 refdes=CD1006 T 61400 55100 5 10 0 1 0 0 1 footprint=0402 T 61400 55000 5 10 1 1 90 0 1 value=0.1uF } C 62200 55100 1 90 0 EMBEDDEDcapacitor-1.sym [ P 62000 55100 62000 55300 1 0 0 { T 61950 55250 5 8 0 1 90 6 1 pinnumber=1 T 62050 55250 5 8 0 1 90 8 1 pinseq=1 T 62000 55300 9 8 0 1 90 0 1 pinlabel=1 T 62000 55300 5 8 0 1 90 2 1 pintype=pas } P 62000 56000 62000 55800 1 0 0 { T 61950 55850 5 8 0 1 90 0 1 pinnumber=2 T 62050 55850 5 8 0 1 90 2 1 pinseq=2 T 62000 55800 9 8 0 1 90 6 1 pinlabel=2 T 62000 55800 5 8 0 1 90 8 1 pintype=pas } L 61800 55500 62200 55500 3 0 0 0 -1 -1 L 61800 55600 62200 55600 3 0 0 0 -1 -1 L 62000 55800 62000 55600 3 0 0 0 -1 -1 L 62000 55500 62000 55300 3 0 0 0 -1 -1 T 61500 55300 5 10 0 0 90 0 1 device=CAPACITOR T 61700 55300 8 10 0 1 90 0 1 refdes=C? T 60900 55300 5 10 0 0 90 0 1 description=capacitor T 61100 55300 5 10 0 0 90 0 1 numslots=0 T 61300 55300 5 10 0 0 90 0 1 symversion=0.1 ] { T 61500 55300 5 10 0 0 90 0 1 device=CAPACITOR T 61700 55300 5 10 1 1 90 0 1 refdes=CD1007 T 62200 55100 5 10 0 1 0 0 1 footprint=0402 T 62200 55000 5 10 1 1 90 0 1 value=0.1uF } N 60400 55000 60400 55100 4 N 62000 55000 62000 55100 4 N 61200 55000 61200 55100 4 N 60400 56000 60400 56100 4 N 61200 56100 61200 56000 4 N 62000 56100 62000 56000 4 N 61600 56100 61600 56200 4 N 61600 54900 61600 55000 4 C 61700 53600 1 0 0 EMBEDDEDgeneric-power.sym [ P 61900 53600 61900 53800 1 0 0 { T 61950 53650 5 6 0 1 0 0 1 pinnumber=1 T 61950 53650 5 6 0 0 0 0 1 pinseq=1 T 61950 53650 5 6 0 1 0 0 1 pinlabel=1 T 61950 53650 5 6 0 1 0 0 1 pintype=pwr } L 61750 53800 62050 53800 3 0 0 0 -1 -1 T 61900 53850 8 10 0 1 0 3 1 net=Vcc:1 ] { T 61900 53850 5 10 1 1 0 3 1 net=VCC33:1 } C 62100 52500 1 90 0 EMBEDDEDcapacitor-1.sym [ P 61900 52500 61900 52700 1 0 0 { T 61850 52650 5 8 0 1 90 6 1 pinnumber=1 T 61950 52650 5 8 0 1 90 8 1 pinseq=1 T 61900 52700 9 8 0 1 90 0 1 pinlabel=1 T 61900 52700 5 8 0 1 90 2 1 pintype=pas } P 61900 53400 61900 53200 1 0 0 { T 61850 53250 5 8 0 1 90 0 1 pinnumber=2 T 61950 53250 5 8 0 1 90 2 1 pinseq=2 T 61900 53200 9 8 0 1 90 6 1 pinlabel=2 T 61900 53200 5 8 0 1 90 8 1 pintype=pas } L 61700 52900 62100 52900 3 0 0 0 -1 -1 L 61700 53000 62100 53000 3 0 0 0 -1 -1 L 61900 53200 61900 53000 3 0 0 0 -1 -1 L 61900 52900 61900 52700 3 0 0 0 -1 -1 T 61400 52700 5 10 0 0 90 0 1 device=CAPACITOR T 61600 52700 8 10 0 1 90 0 1 refdes=C? T 60800 52700 5 10 0 0 90 0 1 description=capacitor T 61000 52700 5 10 0 0 90 0 1 numslots=0 T 61200 52700 5 10 0 0 90 0 1 symversion=0.1 ] { T 61400 52700 5 10 0 0 90 0 1 device=CAPACITOR T 61600 52700 5 10 1 1 90 0 1 refdes=CD1008 T 62100 52500 5 10 0 1 0 0 1 footprint=0402 T 62100 52400 5 10 1 1 90 0 1 value=0.1uF } N 61900 52300 61900 52500 4 N 61900 53400 61900 53600 4 C 52500 41700 1 90 0 EMBEDDEDcapacitor-1.sym [ P 52300 41700 52300 41900 1 0 0 { T 52250 41850 5 8 0 1 90 6 1 pinnumber=1 T 52350 41850 5 8 0 1 90 8 1 pinseq=1 T 52300 41900 9 8 0 1 90 0 1 pinlabel=1 T 52300 41900 5 8 0 1 90 2 1 pintype=pas } P 52300 42600 52300 42400 1 0 0 { T 52250 42450 5 8 0 1 90 0 1 pinnumber=2 T 52350 42450 5 8 0 1 90 2 1 pinseq=2 T 52300 42400 9 8 0 1 90 6 1 pinlabel=2 T 52300 42400 5 8 0 1 90 8 1 pintype=pas } L 52100 42100 52500 42100 3 0 0 0 -1 -1 L 52100 42200 52500 42200 3 0 0 0 -1 -1 L 52300 42400 52300 42200 3 0 0 0 -1 -1 L 52300 42100 52300 41900 3 0 0 0 -1 -1 T 51800 41900 5 10 0 0 90 0 1 device=CAPACITOR T 52000 41900 8 10 0 1 90 0 1 refdes=C? T 51200 41900 5 10 0 0 90 0 1 description=capacitor T 51400 41900 5 10 0 0 90 0 1 numslots=0 T 51600 41900 5 10 0 0 90 0 1 symversion=0.1 ] { T 51800 41900 5 10 0 0 90 0 1 device=CAPACITOR T 52100 41900 5 10 1 1 90 0 1 refdes=C104 T 52500 41700 5 10 0 1 0 0 1 footprint=0402 T 52700 41800 5 10 1 1 90 0 1 value=0.47uF } N 52300 42600 52300 42800 4 N 52300 41700 52300 41600 4 N 51900 41600 52700 41600 4 N 56800 54900 56800 55000 4 C 52200 41200 1 0 0 EMBEDDEDgnd-1.sym [ P 52300 41300 52300 41500 1 0 1 { T 52358 41361 5 4 0 1 0 0 1 pinnumber=1 T 52358 41361 5 4 0 0 0 0 1 pinseq=1 T 52358 41361 5 4 0 1 0 0 1 pinlabel=1 T 52358 41361 5 4 0 1 0 0 1 pintype=pwr } L 52200 41300 52400 41300 3 0 0 0 -1 -1 L 52255 41250 52345 41250 3 0 0 0 -1 -1 L 52280 41210 52320 41210 3 0 0 0 -1 -1 T 52500 41250 8 10 0 0 0 0 1 net=GND:1 ] { T 52000 41000 5 10 1 1 0 0 1 net=GND:1 } N 52300 41600 52300 41500 4 T 58100 41200 9 10 1 0 0 0 1 Beta4 Rapid Measurement - Digital Components T 61900 40900 9 10 1 0 0 0 1 1 T 61900 40600 9 10 1 0 0 0 1 Andrew H. Armenia C 56600 45600 1 0 0 EMBEDDEDgnd-1.sym [ P 56700 45700 56700 45900 1 0 1 { T 56758 45761 5 4 0 1 0 0 1 pinnumber=1 T 56758 45761 5 4 0 0 0 0 1 pinseq=1 T 56758 45761 5 4 0 1 0 0 1 pinlabel=1 T 56758 45761 5 4 0 1 0 0 1 pintype=pwr } L 56600 45700 56800 45700 3 0 0 0 -1 -1 L 56655 45650 56745 45650 3 0 0 0 -1 -1 L 56680 45610 56720 45610 3 0 0 0 -1 -1 T 56900 45650 8 10 0 0 0 0 1 net=GND:1 ] { T 56400 45400 5 10 1 1 0 0 1 net=GND:1 } C 57900 47100 1 0 0 EMBEDDEDgnd-1.sym [ P 58000 47200 58000 47400 1 0 1 { T 58058 47261 5 4 0 1 0 0 1 pinnumber=1 T 58058 47261 5 4 0 0 0 0 1 pinseq=1 T 58058 47261 5 4 0 1 0 0 1 pinlabel=1 T 58058 47261 5 4 0 1 0 0 1 pintype=pwr } L 57900 47200 58100 47200 3 0 0 0 -1 -1 L 57955 47150 58045 47150 3 0 0 0 -1 -1 L 57980 47110 58020 47110 3 0 0 0 -1 -1 T 58200 47150 8 10 0 0 0 0 1 net=GND:1 ] { T 57700 46900 5 10 1 1 0 0 1 net=GND:1 } C 60900 48000 1 0 0 EMBEDDEDgnd-1.sym [ P 61000 48100 61000 48300 1 0 1 { T 61058 48161 5 4 0 1 0 0 1 pinnumber=1 T 61058 48161 5 4 0 0 0 0 1 pinseq=1 T 61058 48161 5 4 0 1 0 0 1 pinlabel=1 T 61058 48161 5 4 0 1 0 0 1 pintype=pwr } L 60900 48100 61100 48100 3 0 0 0 -1 -1 L 60955 48050 61045 48050 3 0 0 0 -1 -1 L 60980 48010 61020 48010 3 0 0 0 -1 -1 T 61200 48050 8 10 0 0 0 0 1 net=GND:1 ] { T 60700 47800 5 10 1 1 0 0 1 net=GND:1 } C 61800 52000 1 0 0 EMBEDDEDgnd-1.sym [ P 61900 52100 61900 52300 1 0 1 { T 61958 52161 5 4 0 1 0 0 1 pinnumber=1 T 61958 52161 5 4 0 0 0 0 1 pinseq=1 T 61958 52161 5 4 0 1 0 0 1 pinlabel=1 T 61958 52161 5 4 0 1 0 0 1 pintype=pwr } L 61800 52100 62000 52100 3 0 0 0 -1 -1 L 61855 52050 61945 52050 3 0 0 0 -1 -1 L 61880 52010 61920 52010 3 0 0 0 -1 -1 T 62100 52050 8 10 0 0 0 0 1 net=GND:1 ] { T 61600 51800 5 10 1 1 0 0 1 net=GND:1 } C 56700 54600 1 0 0 EMBEDDEDgnd-1.sym [ P 56800 54700 56800 54900 1 0 1 { T 56858 54761 5 4 0 1 0 0 1 pinnumber=1 T 56858 54761 5 4 0 0 0 0 1 pinseq=1 T 56858 54761 5 4 0 1 0 0 1 pinlabel=1 T 56858 54761 5 4 0 1 0 0 1 pintype=pwr } L 56700 54700 56900 54700 3 0 0 0 -1 -1 L 56755 54650 56845 54650 3 0 0 0 -1 -1 L 56780 54610 56820 54610 3 0 0 0 -1 -1 T 57000 54650 8 10 0 0 0 0 1 net=GND:1 ] { T 56500 54400 5 10 1 1 0 0 1 net=GND:1 } C 61500 54600 1 0 0 EMBEDDEDgnd-1.sym [ P 61600 54700 61600 54900 1 0 1 { T 61658 54761 5 4 0 1 0 0 1 pinnumber=1 T 61658 54761 5 4 0 0 0 0 1 pinseq=1 T 61658 54761 5 4 0 1 0 0 1 pinlabel=1 T 61658 54761 5 4 0 1 0 0 1 pintype=pwr } L 61500 54700 61700 54700 3 0 0 0 -1 -1 L 61555 54650 61645 54650 3 0 0 0 -1 -1 L 61580 54610 61620 54610 3 0 0 0 -1 -1 T 61800 54650 8 10 0 0 0 0 1 net=GND:1 ] { T 61300 54400 5 10 1 1 0 0 1 net=GND:1 } C 45900 48600 1 0 0 EMBEDDEDgnd-1.sym [ P 46000 48700 46000 48900 1 0 1 { T 46058 48761 5 4 0 1 0 0 1 pinnumber=1 T 46058 48761 5 4 0 0 0 0 1 pinseq=1 T 46058 48761 5 4 0 1 0 0 1 pinlabel=1 T 46058 48761 5 4 0 1 0 0 1 pintype=pwr } L 45900 48700 46100 48700 3 0 0 0 -1 -1 L 45955 48650 46045 48650 3 0 0 0 -1 -1 L 45980 48610 46020 48610 3 0 0 0 -1 -1 T 46200 48650 8 10 0 0 0 0 1 net=GND:1 ] { T 45700 48400 5 10 1 1 0 0 1 net=GND:1 } N 52500 54000 52500 53400 4 N 52300 54200 52300 54000 4 N 57400 44700 57400 45100 4 N 62000 55000 60400 55000 4 N 60400 56100 62000 56100 4 N 53700 54000 52500 54000 4 N 55600 48300 54600 48300 4 { T 54600 48300 5 10 1 1 0 0 1 netname=\_RST\_ } N 54600 47500 55400 47500 4 { T 54600 47500 5 10 1 1 0 0 1 netname=TEST } C 45800 48700 1 0 1 EMBEDDEDconnector5-2.sym [ T 45100 51200 8 10 0 1 0 0 1 refdes=CONN? T 45500 51150 5 10 0 0 0 6 1 device=CONNECTOR_5 T 45500 51350 5 10 0 0 0 6 1 footprint=SIP5N T 45500 51550 5 10 0 0 0 6 1 author=Leon Kos T 45500 51750 5 10 0 0 0 6 1 description=generic connector T 45500 51950 5 10 0 0 0 6 1 numslots=0 P 45800 50700 45600 50700 1 0 0 { T 45600 50750 5 8 0 1 0 0 1 pinnumber=1 T 45600 50650 5 8 0 1 0 2 1 pinseq=1 T 45450 50700 9 8 1 1 0 6 1 pinlabel=1 T 45450 50700 5 8 0 1 0 8 1 pintype=pas } V 45550 50700 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 P 45800 50300 45600 50300 1 0 0 { T 45600 50350 5 8 0 1 0 0 1 pinnumber=2 T 45600 50250 5 8 0 1 0 2 1 pinseq=2 T 45450 50300 9 8 1 1 0 6 1 pinlabel=2 T 45450 50300 5 8 0 1 0 8 1 pintype=pas } V 45550 50300 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 P 45800 49900 45600 49900 1 0 0 { T 45600 49950 5 8 0 1 0 0 1 pinnumber=3 T 45600 49850 5 8 0 1 0 2 1 pinseq=3 T 45450 49900 9 8 1 1 0 6 1 pinlabel=3 T 45450 49900 5 8 0 1 0 8 1 pintype=pas } V 45550 49900 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 P 45800 49500 45600 49500 1 0 0 { T 45600 49550 5 8 0 1 0 0 1 pinnumber=4 T 45600 49450 5 8 0 1 0 2 1 pinseq=4 T 45450 49500 9 8 1 1 0 6 1 pinlabel=4 T 45450 49500 5 8 0 1 0 8 1 pintype=pas } V 45550 49500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 P 45800 49100 45600 49100 1 0 0 { T 45600 49150 5 8 0 1 0 0 1 pinnumber=5 T 45600 49050 5 8 0 1 0 2 1 pinseq=5 T 45450 49100 9 8 1 1 0 6 1 pinlabel=5 T 45450 49100 5 8 0 1 0 8 1 pintype=pas } V 45550 49100 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 B 45100 48700 400 2400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 ] { T 45100 51200 5 10 1 1 0 0 1 refdes=J100 T 45500 51150 5 10 0 0 0 6 1 device=CONNECTOR_5 T 45500 51350 5 10 0 0 0 6 1 footprint=5PICOBLADE } N 45800 49500 46400 49500 4 { T 45800 49500 5 10 1 1 0 0 1 netname=\_RST\_ } N 45800 49900 46400 49900 4 { T 45800 49900 5 10 1 1 0 0 1 netname=TEST } N 61000 48500 61400 48500 4 N 62000 49900 62900 49900 4 C 45900 40700 1 0 1 EMBEDDEDconnector18-2.sym [ T 45100 48500 8 10 0 1 0 0 1 refdes=CONN? T 45500 48450 5 10 0 0 0 6 1 device=CONNECTOR_18 T 45500 48650 5 10 0 0 0 6 1 footprint=SIP18N T 45500 48850 5 10 0 0 0 6 1 author=Leon Kos T 45500 49050 5 10 0 0 0 6 1 description=generic connector T 45500 49250 5 10 0 0 0 6 1 numslots=0 P 45800 48000 45600 48000 1 0 0 { T 45600 48050 5 8 0 1 0 0 1 pinnumber=1 T 45600 47950 5 8 0 1 0 2 1 pinseq=1 T 45450 48000 9 8 1 1 0 6 1 pinlabel=1 T 45450 48000 5 8 0 1 0 8 1 pintype=pas } V 45550 48000 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 P 45800 47600 45600 47600 1 0 0 { T 45600 47650 5 8 0 1 0 0 1 pinnumber=2 T 45600 47550 5 8 0 1 0 2 1 pinseq=2 T 45450 47600 9 8 1 1 0 6 1 pinlabel=2 T 45450 47600 5 8 0 1 0 8 1 pintype=pas } V 45550 47600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 P 45800 47200 45600 47200 1 0 0 { T 45600 47250 5 8 0 1 0 0 1 pinnumber=3 T 45600 47150 5 8 0 1 0 2 1 pinseq=3 T 45450 47200 9 8 1 1 0 6 1 pinlabel=3 T 45450 47200 5 8 0 1 0 8 1 pintype=pas } V 45550 47200 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 P 45800 46800 45600 46800 1 0 0 { T 45600 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45150 5 8 0 1 0 2 1 pinseq=8 T 45450 45200 9 8 1 1 0 6 1 pinlabel=8 T 45450 45200 5 8 0 1 0 8 1 pintype=pas } V 45550 45200 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 P 45800 44800 45600 44800 1 0 0 { T 45600 44850 5 8 0 1 0 0 1 pinnumber=9 T 45600 44750 5 8 0 1 0 2 1 pinseq=9 T 45450 44800 9 8 1 1 0 6 1 pinlabel=9 T 45450 44800 5 8 0 1 0 8 1 pintype=pas } V 45550 44800 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 P 45800 44400 45600 44400 1 0 0 { T 45600 44450 5 8 0 1 0 0 1 pinnumber=10 T 45600 44350 5 8 0 1 0 2 1 pinseq=10 T 45450 44400 9 8 1 1 0 6 1 pinlabel=10 T 45450 44400 5 8 0 1 0 8 1 pintype=pas } V 45550 44400 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 P 45800 44000 45600 44000 1 0 0 { T 45600 44050 5 8 0 1 0 0 1 pinnumber=11 T 45600 43950 5 8 0 1 0 2 1 pinseq=11 T 45450 44000 9 8 1 1 0 6 1 pinlabel=11 T 45450 44000 5 8 0 1 0 8 1 pintype=pas } V 45550 44000 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 P 45800 43600 45600 43600 1 0 0 { T 45600 43650 5 8 0 1 0 0 1 pinnumber=12 T 45600 43550 5 8 0 1 0 2 1 pinseq=12 T 45450 43600 9 8 1 1 0 6 1 pinlabel=12 T 45450 43600 5 8 0 1 0 8 1 pintype=pas } V 45550 43600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 P 45800 43200 45600 43200 1 0 0 { T 45600 43250 5 8 0 1 0 0 1 pinnumber=13 T 45600 43150 5 8 0 1 0 2 1 pinseq=13 T 45450 43200 9 8 1 1 0 6 1 pinlabel=13 T 45450 43200 5 8 0 1 0 8 1 pintype=pas } V 45550 43200 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 P 45800 42800 45600 42800 1 0 0 { T 45600 42850 5 8 0 1 0 0 1 pinnumber=14 T 45600 42750 5 8 0 1 0 2 1 pinseq=14 T 45450 42800 9 8 1 1 0 6 1 pinlabel=14 T 45450 42800 5 8 0 1 0 8 1 pintype=pas } V 45550 42800 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 P 45800 42400 45600 42400 1 0 0 { T 45600 42450 5 8 0 1 0 0 1 pinnumber=15 T 45600 42350 5 8 0 1 0 2 1 pinseq=15 T 45450 42400 9 8 1 1 0 6 1 pinlabel=15 T 45450 42400 5 8 0 1 0 8 1 pintype=pas } V 45550 42400 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 P 45800 42000 45600 42000 1 0 0 { T 45600 42050 5 8 0 1 0 0 1 pinnumber=16 T 45600 41950 5 8 0 1 0 2 1 pinseq=16 T 45450 42000 9 8 1 1 0 6 1 pinlabel=16 T 45450 42000 5 8 0 1 0 8 1 pintype=pas } V 45550 42000 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 P 45800 41600 45600 41600 1 0 0 { T 45600 41650 5 8 0 1 0 0 1 pinnumber=17 T 45600 41550 5 8 0 1 0 2 1 pinseq=17 T 45450 41600 9 8 1 1 0 6 1 pinlabel=17 T 45450 41600 5 8 0 1 0 8 1 pintype=pas } V 45550 41600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 P 45800 41200 45600 41200 1 0 0 { T 45600 41250 5 8 0 1 0 0 1 pinnumber=18 T 45600 41150 5 8 0 1 0 2 1 pinseq=18 T 45450 41200 9 8 1 1 0 6 1 pinlabel=18 T 45450 41200 5 8 0 1 0 8 1 pintype=pas } V 45550 41200 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 B 45100 40800 400 7600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 ] { T 45100 48500 5 10 1 1 0 0 1 refdes=J101 T 45500 48450 5 10 0 0 0 6 1 device=CONNECTOR_18 T 45500 48650 5 10 0 0 0 6 1 footprint=HEADER18_2 } U 47400 52900 47400 40800 10 -1 N 45800 50300 47200 50300 4 { T 45800 50300 5 10 1 1 0 0 1 netname=P1.6 } C 47200 50300 1 270 0 EMBEDDEDbusripper-1.sym [ T 47600 50300 5 8 0 0 270 0 1 device=none P 47200 50300 47300 50200 1 0 0 { T 47700 50300 5 8 0 0 270 0 1 pinseq=1 T 47800 50300 5 8 0 0 270 0 1 pinnumber=1 T 47900 50300 5 8 0 0 270 0 1 pintype=pas T 48000 50300 5 8 0 0 270 0 1 pinlabel=netside } T 47500 50300 5 8 0 0 270 0 1 graphical=1 L 47400 50100 47300 50200 10 30 0 0 -1 -1 ] { T 47600 50300 5 8 0 0 270 0 1 device=none } N 50000 50300 47600 50300 4 { T 49600 50300 5 10 1 1 0 0 1 netname=P1.6 } C 47600 50300 1 180 0 EMBEDDEDbusripper-1.sym [ T 47600 49900 5 8 0 0 180 0 1 device=none P 47600 50300 47500 50200 1 0 0 { T 47600 49800 5 8 0 0 180 0 1 pinseq=1 T 47600 49700 5 8 0 0 180 0 1 pinnumber=1 T 47600 49600 5 8 0 0 180 0 1 pintype=pas T 47600 49500 5 8 0 0 180 0 1 pinlabel=netside } T 47600 50000 5 8 0 0 180 0 1 graphical=1 L 47400 50100 47500 50200 10 30 0 0 -1 -1 ] { T 47600 49900 5 8 0 0 180 0 1 device=none } N 50000 50700 47600 50700 4 { T 49600 50700 5 10 1 1 0 0 1 netname=P1.5 } C 47600 50700 1 180 0 EMBEDDEDbusripper-1.sym [ T 47600 50300 5 8 0 0 180 0 1 device=none P 47600 50700 47500 50600 1 0 0 { T 47600 50200 5 8 0 0 180 0 1 pinseq=1 T 47600 50100 5 8 0 0 180 0 1 pinnumber=1 T 47600 50000 5 8 0 0 180 0 1 pintype=pas T 47600 49900 5 8 0 0 180 0 1 pinlabel=netside } T 47600 50400 5 8 0 0 180 0 1 graphical=1 L 47400 50500 47500 50600 10 30 0 0 -1 -1 ] { T 47600 50300 5 8 0 0 180 0 1 device=none } N 45800 50700 47200 50700 4 { T 45800 50700 5 10 1 1 0 0 1 netname=P1.5 } C 47200 50700 1 270 0 EMBEDDEDbusripper-1.sym [ T 47600 50700 5 8 0 0 270 0 1 device=none P 47200 50700 47300 50600 1 0 0 { T 47700 50700 5 8 0 0 270 0 1 pinseq=1 T 47800 50700 5 8 0 0 270 0 1 pinnumber=1 T 47900 50700 5 8 0 0 270 0 1 pintype=pas T 48000 50700 5 8 0 0 270 0 1 pinlabel=netside } T 47500 50700 5 8 0 0 270 0 1 graphical=1 L 47400 50500 47300 50600 10 30 0 0 -1 -1 ] { T 47600 50700 5 8 0 0 270 0 1 device=none } N 50000 51100 47600 51100 4 { T 49600 51100 5 10 1 1 0 0 1 netname=P1.4 } C 47600 51100 1 180 0 EMBEDDEDbusripper-1.sym [ T 47600 50700 5 8 0 0 180 0 1 device=none P 47600 51100 47500 51000 1 0 0 { T 47600 50600 5 8 0 0 180 0 1 pinseq=1 T 47600 50500 5 8 0 0 180 0 1 pinnumber=1 T 47600 50400 5 8 0 0 180 0 1 pintype=pas T 47600 50300 5 8 0 0 180 0 1 pinlabel=netside } T 47600 50800 5 8 0 0 180 0 1 graphical=1 L 47400 50900 47500 51000 10 30 0 0 -1 -1 ] { T 47600 50700 5 8 0 0 180 0 1 device=none } N 50000 51500 47600 51500 4 { T 49600 51500 5 10 1 1 0 0 1 netname=P1.3 } C 47600 51500 1 180 0 EMBEDDEDbusripper-1.sym [ T 47600 51100 5 8 0 0 180 0 1 device=none P 47600 51500 47500 51400 1 0 0 { T 47600 51000 5 8 0 0 180 0 1 pinseq=1 T 47600 50900 5 8 0 0 180 0 1 pinnumber=1 T 47600 50800 5 8 0 0 180 0 1 pintype=pas T 47600 50700 5 8 0 0 180 0 1 pinlabel=netside } T 47600 51200 5 8 0 0 180 0 1 graphical=1 L 47400 51300 47500 51400 10 30 0 0 -1 -1 ] { T 47600 51100 5 8 0 0 180 0 1 device=none } N 50000 51900 47600 51900 4 { T 49600 51900 5 10 1 1 0 0 1 netname=P1.2 } C 47600 51900 1 180 0 EMBEDDEDbusripper-1.sym [ T 47600 51500 5 8 0 0 180 0 1 device=none P 47600 51900 47500 51800 1 0 0 { T 47600 51400 5 8 0 0 180 0 1 pinseq=1 T 47600 51300 5 8 0 0 180 0 1 pinnumber=1 T 47600 51200 5 8 0 0 180 0 1 pintype=pas T 47600 51100 5 8 0 0 180 0 1 pinlabel=netside } T 47600 51600 5 8 0 0 180 0 1 graphical=1 L 47400 51700 47500 51800 10 30 0 0 -1 -1 ] { T 47600 51500 5 8 0 0 180 0 1 device=none } N 50000 52300 47600 52300 4 { T 49600 52300 5 10 1 1 0 0 1 netname=P1.1 } C 47600 52300 1 180 0 EMBEDDEDbusripper-1.sym [ T 47600 51900 5 8 0 0 180 0 1 device=none P 47600 52300 47500 52200 1 0 0 { T 47600 51800 5 8 0 0 180 0 1 pinseq=1 T 47600 51700 5 8 0 0 180 0 1 pinnumber=1 T 47600 51600 5 8 0 0 180 0 1 pintype=pas T 47600 51500 5 8 0 0 180 0 1 pinlabel=netside } T 47600 52000 5 8 0 0 180 0 1 graphical=1 L 47400 52100 47500 52200 10 30 0 0 -1 -1 ] { T 47600 51900 5 8 0 0 180 0 1 device=none } N 50000 52700 47600 52700 4 { T 49600 52700 5 10 1 1 0 0 1 netname=P1.0 } C 47600 52700 1 180 0 EMBEDDEDbusripper-1.sym [ T 47600 52300 5 8 0 0 180 0 1 device=none P 47600 52700 47500 52600 1 0 0 { T 47600 52200 5 8 0 0 180 0 1 pinseq=1 T 47600 52100 5 8 0 0 180 0 1 pinnumber=1 T 47600 52000 5 8 0 0 180 0 1 pintype=pas T 47600 51900 5 8 0 0 180 0 1 pinlabel=netside } T 47600 52400 5 8 0 0 180 0 1 graphical=1 L 47400 52500 47500 52600 10 30 0 0 -1 -1 ] { T 47600 52300 5 8 0 0 180 0 1 device=none } N 50000 49900 47600 49900 4 { T 49600 49900 5 10 1 1 0 0 1 netname=P1.7 } C 47600 49900 1 180 0 EMBEDDEDbusripper-1.sym [ T 47600 49500 5 8 0 0 180 0 1 device=none P 47600 49900 47500 49800 1 0 0 { T 47600 49400 5 8 0 0 180 0 1 pinseq=1 T 47600 49300 5 8 0 0 180 0 1 pinnumber=1 T 47600 49200 5 8 0 0 180 0 1 pintype=pas T 47600 49100 5 8 0 0 180 0 1 pinlabel=netside } T 47600 49600 5 8 0 0 180 0 1 graphical=1 L 47400 49700 47500 49800 10 30 0 0 -1 -1 ] { T 47600 49500 5 8 0 0 180 0 1 device=none } N 50000 49500 47600 49500 4 { T 49600 49500 5 10 1 1 0 0 1 netname=P2.0 } C 47600 49500 1 180 0 EMBEDDEDbusripper-1.sym [ T 47600 49100 5 8 0 0 180 0 1 device=none P 47600 49500 47500 49400 1 0 0 { T 47600 49000 5 8 0 0 180 0 1 pinseq=1 T 47600 48900 5 8 0 0 180 0 1 pinnumber=1 T 47600 48800 5 8 0 0 180 0 1 pintype=pas T 47600 48700 5 8 0 0 180 0 1 pinlabel=netside } T 47600 49200 5 8 0 0 180 0 1 graphical=1 L 47400 49300 47500 49400 10 30 0 0 -1 -1 ] { T 47600 49100 5 8 0 0 180 0 1 device=none } N 50000 49100 47600 49100 4 { T 49600 49100 5 10 1 1 0 0 1 netname=P2.1 } C 47600 49100 1 180 0 EMBEDDEDbusripper-1.sym [ T 47600 48700 5 8 0 0 180 0 1 device=none P 47600 49100 47500 49000 1 0 0 { T 47600 48600 5 8 0 0 180 0 1 pinseq=1 T 47600 48500 5 8 0 0 180 0 1 pinnumber=1 T 47600 48400 5 8 0 0 180 0 1 pintype=pas T 47600 48300 5 8 0 0 180 0 1 pinlabel=netside } T 47600 48800 5 8 0 0 180 0 1 graphical=1 L 47400 48900 47500 49000 10 30 0 0 -1 -1 ] { T 47600 48700 5 8 0 0 180 0 1 device=none } N 50000 48700 47600 48700 4 { T 49600 48700 5 10 1 1 0 0 1 netname=P2.2 } C 47600 48700 1 180 0 EMBEDDEDbusripper-1.sym [ T 47600 48300 5 8 0 0 180 0 1 device=none P 47600 48700 47500 48600 1 0 0 { T 47600 48200 5 8 0 0 180 0 1 pinseq=1 T 47600 48100 5 8 0 0 180 0 1 pinnumber=1 T 47600 48000 5 8 0 0 180 0 1 pintype=pas T 47600 47900 5 8 0 0 180 0 1 pinlabel=netside } T 47600 48400 5 8 0 0 180 0 1 graphical=1 L 47400 48500 47500 48600 10 30 0 0 -1 -1 ] { T 47600 48300 5 8 0 0 180 0 1 device=none } N 50000 48300 47600 48300 4 { T 49600 48300 5 10 1 1 0 0 1 netname=P2.3 } C 47600 48300 1 180 0 EMBEDDEDbusripper-1.sym [ T 47600 47900 5 8 0 0 180 0 1 device=none P 47600 48300 47500 48200 1 0 0 { T 47600 47800 5 8 0 0 180 0 1 pinseq=1 T 47600 47700 5 8 0 0 180 0 1 pinnumber=1 T 47600 47600 5 8 0 0 180 0 1 pintype=pas T 47600 47500 5 8 0 0 180 0 1 pinlabel=netside } T 47600 48000 5 8 0 0 180 0 1 graphical=1 L 47400 48100 47500 48200 10 30 0 0 -1 -1 ] { T 47600 47900 5 8 0 0 180 0 1 device=none } N 50000 47900 47600 47900 4 { T 49600 47900 5 10 1 1 0 0 1 netname=P2.4 } C 47600 47900 1 180 0 EMBEDDEDbusripper-1.sym [ T 47600 47500 5 8 0 0 180 0 1 device=none P 47600 47900 47500 47800 1 0 0 { T 47600 47400 5 8 0 0 180 0 1 pinseq=1 T 47600 47300 5 8 0 0 180 0 1 pinnumber=1 T 47600 47200 5 8 0 0 180 0 1 pintype=pas T 47600 47100 5 8 0 0 180 0 1 pinlabel=netside } T 47600 47600 5 8 0 0 180 0 1 graphical=1 L 47400 47700 47500 47800 10 30 0 0 -1 -1 ] { T 47600 47500 5 8 0 0 180 0 1 device=none } N 50000 47500 47600 47500 4 { T 49600 47500 5 10 1 1 0 0 1 netname=P2.5 } C 47600 47500 1 180 0 EMBEDDEDbusripper-1.sym [ T 47600 47100 5 8 0 0 180 0 1 device=none P 47600 47500 47500 47400 1 0 0 { T 47600 47000 5 8 0 0 180 0 1 pinseq=1 T 47600 46900 5 8 0 0 180 0 1 pinnumber=1 T 47600 46800 5 8 0 0 180 0 1 pintype=pas T 47600 46700 5 8 0 0 180 0 1 pinlabel=netside } T 47600 47200 5 8 0 0 180 0 1 graphical=1 L 47400 47300 47500 47400 10 30 0 0 -1 -1 ] { T 47600 47100 5 8 0 0 180 0 1 device=none } N 50000 47100 47600 47100 4 { T 49600 47100 5 10 1 1 0 0 1 netname=P2.6 } C 47600 47100 1 180 0 EMBEDDEDbusripper-1.sym [ T 47600 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44400 1 270 0 EMBEDDEDbusripper-1.sym [ T 47600 44400 5 8 0 0 270 0 1 device=none P 47200 44400 47300 44300 1 0 0 { T 47700 44400 5 8 0 0 270 0 1 pinseq=1 T 47800 44400 5 8 0 0 270 0 1 pinnumber=1 T 47900 44400 5 8 0 0 270 0 1 pintype=pas T 48000 44400 5 8 0 0 270 0 1 pinlabel=netside } T 47500 44400 5 8 0 0 270 0 1 graphical=1 L 47400 44200 47300 44300 10 30 0 0 -1 -1 ] { T 47600 44400 5 8 0 0 270 0 1 device=none } N 45800 44000 47200 44000 4 { T 45800 44000 5 10 1 1 0 0 1 netname=P2.1 } C 47200 44000 1 270 0 EMBEDDEDbusripper-1.sym [ T 47600 44000 5 8 0 0 270 0 1 device=none P 47200 44000 47300 43900 1 0 0 { T 47700 44000 5 8 0 0 270 0 1 pinseq=1 T 47800 44000 5 8 0 0 270 0 1 pinnumber=1 T 47900 44000 5 8 0 0 270 0 1 pintype=pas T 48000 44000 5 8 0 0 270 0 1 pinlabel=netside } T 47500 44000 5 8 0 0 270 0 1 graphical=1 L 47400 43800 47300 43900 10 30 0 0 -1 -1 ] { T 47600 44000 5 8 0 0 270 0 1 device=none } N 45800 43600 47200 43600 4 { T 45800 43600 5 10 1 1 0 0 1 netname=P2.2 } C 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} C 47200 42800 1 270 0 EMBEDDEDbusripper-1.sym [ T 47600 42800 5 8 0 0 270 0 1 device=none P 47200 42800 47300 42700 1 0 0 { T 47700 42800 5 8 0 0 270 0 1 pinseq=1 T 47800 42800 5 8 0 0 270 0 1 pinnumber=1 T 47900 42800 5 8 0 0 270 0 1 pintype=pas T 48000 42800 5 8 0 0 270 0 1 pinlabel=netside } T 47500 42800 5 8 0 0 270 0 1 graphical=1 L 47400 42600 47300 42700 10 30 0 0 -1 -1 ] { T 47600 42800 5 8 0 0 270 0 1 device=none } N 45800 42400 47200 42400 4 { T 45800 42400 5 10 1 1 0 0 1 netname=P2.5 } C 47200 42400 1 270 0 EMBEDDEDbusripper-1.sym [ T 47600 42400 5 8 0 0 270 0 1 device=none P 47200 42400 47300 42300 1 0 0 { T 47700 42400 5 8 0 0 270 0 1 pinseq=1 T 47800 42400 5 8 0 0 270 0 1 pinnumber=1 T 47900 42400 5 8 0 0 270 0 1 pintype=pas T 48000 42400 5 8 0 0 270 0 1 pinlabel=netside } T 47500 42400 5 8 0 0 270 0 1 graphical=1 L 47400 42200 47300 42300 10 30 0 0 -1 -1 ] { T 47600 42400 5 8 0 0 270 0 1 device=none } N 45800 42000 47200 42000 4 { T 45800 42000 5 10 1 1 0 0 1 netname=P2.6 } C 47200 42000 1 270 0 EMBEDDEDbusripper-1.sym [ T 47600 42000 5 8 0 0 270 0 1 device=none P 47200 42000 47300 41900 1 0 0 { T 47700 42000 5 8 0 0 270 0 1 pinseq=1 T 47800 42000 5 8 0 0 270 0 1 pinnumber=1 T 47900 42000 5 8 0 0 270 0 1 pintype=pas T 48000 42000 5 8 0 0 270 0 1 pinlabel=netside } T 47500 42000 5 8 0 0 270 0 1 graphical=1 L 47400 41800 47300 41900 10 30 0 0 -1 -1 ] { T 47600 42000 5 8 0 0 270 0 1 device=none } N 45800 41600 47200 41600 4 { T 45800 41600 5 10 1 1 0 0 1 netname=P2.7 } C 47200 41600 1 270 0 EMBEDDEDbusripper-1.sym [ T 47600 41600 5 8 0 0 270 0 1 device=none P 47200 41600 47300 41500 1 0 0 { T 47700 41600 5 8 0 0 270 0 1 pinseq=1 T 47800 41600 5 8 0 0 270 0 1 pinnumber=1 T 47900 41600 5 8 0 0 270 0 1 pintype=pas T 48000 41600 5 8 0 0 270 0 1 pinlabel=netside } T 47500 41600 5 8 0 0 270 0 1 graphical=1 L 47400 41400 47300 41500 10 30 0 0 -1 -1 ] { T 47600 41600 5 8 0 0 270 0 1 device=none } C 46600 48200 1 0 0 EMBEDDEDgeneric-power.sym [ P 46800 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T 54900 52800 5 10 0 0 90 0 1 description=capacitor T 55100 52800 5 10 0 0 90 0 1 numslots=0 T 55300 52800 5 10 0 0 90 0 1 symversion=0.1 ] { T 55500 52800 5 10 0 0 90 0 1 device=CAPACITOR T 55700 52800 5 10 1 1 90 0 1 refdes=C101 T 56200 52600 5 10 0 1 0 0 1 footprint=0402 T 56200 52500 5 10 1 1 90 0 1 value=20pF } C 57500 52600 1 90 0 EMBEDDEDcapacitor-1.sym [ P 57300 52600 57300 52800 1 0 0 { T 57250 52750 5 8 0 1 90 6 1 pinnumber=1 T 57350 52750 5 8 0 1 90 8 1 pinseq=1 T 57300 52800 9 8 0 1 90 0 1 pinlabel=1 T 57300 52800 5 8 0 1 90 2 1 pintype=pas } P 57300 53500 57300 53300 1 0 0 { T 57250 53350 5 8 0 1 90 0 1 pinnumber=2 T 57350 53350 5 8 0 1 90 2 1 pinseq=2 T 57300 53300 9 8 0 1 90 6 1 pinlabel=2 T 57300 53300 5 8 0 1 90 8 1 pintype=pas } L 57100 53000 57500 53000 3 0 0 0 -1 -1 L 57100 53100 57500 53100 3 0 0 0 -1 -1 L 57300 53300 57300 53100 3 0 0 0 -1 -1 L 57300 53000 57300 52800 3 0 0 0 -1 -1 T 56800 52800 5 10 0 0 90 0 1 device=CAPACITOR T 57000 52800 8 10 0 1 90 0 1 refdes=C? T 56200 52800 5 10 0 0 90 0 1 description=capacitor T 56400 52800 5 10 0 0 90 0 1 numslots=0 T 56600 52800 5 10 0 0 90 0 1 symversion=0.1 ] { T 56800 52800 5 10 0 0 90 0 1 device=CAPACITOR T 57100 52800 5 10 1 1 90 0 1 refdes=C103 T 57500 52600 5 10 0 1 0 0 1 footprint=0603 T 57500 52500 5 10 1 1 90 0 1 value=20pF } N 56000 52600 56000 52500 4 N 56000 52500 57300 52500 4 N 57300 53600 56000 53600 4 N 56000 53600 56000 53500 4 N 56700 53700 56700 53600 4 N 57300 53500 57300 53600 4 N 57300 52600 57300 52500 4 N 56700 52400 56700 52500 4 C 56600 52100 1 0 0 EMBEDDEDgnd-1.sym [ P 56700 52200 56700 52400 1 0 1 { T 56758 52261 5 4 0 1 0 0 1 pinnumber=1 T 56758 52261 5 4 0 0 0 0 1 pinseq=1 T 56758 52261 5 4 0 1 0 0 1 pinlabel=1 T 56758 52261 5 4 0 1 0 0 1 pintype=pwr } L 56600 52200 56800 52200 3 0 0 0 -1 -1 L 56655 52150 56745 52150 3 0 0 0 -1 -1 L 56680 52110 56720 52110 3 0 0 0 -1 -1 T 56900 52150 8 10 0 0 0 0 1 net=GND:1 ] { T 56400 51900 5 10 1 1 0 0 1 net=GND:1 } C 55800 52000 1 180 0 EMBEDDEDcrystal-1.sym [ P 55800 51900 55600 51900 1 0 0 { T 55650 51850 5 8 0 1 180 6 1 pinnumber=1 T 55650 51950 5 8 0 1 180 8 1 pinseq=1 T 55550 51900 9 8 0 1 180 0 1 pinlabel=1 T 55550 51900 5 8 0 1 180 2 1 pintype=pas } P 55300 51900 55100 51900 1 0 1 { T 55250 51850 5 8 0 1 180 0 1 pinnumber=2 T 55250 51950 5 8 0 1 180 2 1 pinseq=2 T 55350 51900 9 8 0 1 180 6 1 pinlabel=2 T 55350 51900 5 8 0 1 180 8 1 pintype=pas } B 55350 51800 200 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 T 55600 51500 5 10 0 0 180 0 1 device=CRYSTAL L 55600 51760 55600 52040 3 0 0 0 -1 -1 L 55300 51760 55300 52040 3 0 0 0 -1 -1 T 55600 51700 8 10 0 1 180 0 1 refdes=U? T 55600 50900 5 10 0 0 180 0 1 description=crystal T 55600 51100 5 10 0 0 180 0 1 numslots=0 T 55600 51300 5 10 0 0 180 0 1 symversion=0.1 ] { T 55600 51500 5 10 0 0 180 0 1 device=CRYSTAL T 55600 51700 5 10 1 1 180 0 1 refdes=X100 T 55800 52000 5 10 0 1 0 0 1 footprint=CMJ206T T 55800 52000 5 10 0 0 0 0 1 netname=0.1 } N 54600 52300 56100 52300 4 N 56100 52300 56100 51900 4 N 55800 51900 56100 51900 4 N 55100 51900 54600 51900 4 C 56600 56200 1 0 0 EMBEDDEDgeneric-power.sym [ P 56800 56200 56800 56400 1 0 0 { T 56850 56250 5 6 0 1 0 0 1 pinnumber=1 T 56850 56250 5 6 0 0 0 0 1 pinseq=1 T 56850 56250 5 6 0 1 0 0 1 pinlabel=1 T 56850 56250 5 6 0 1 0 0 1 pintype=pwr } L 56650 56400 56950 56400 3 0 0 0 -1 -1 T 56800 56450 8 10 0 1 0 3 1 net=Vcc:1 ] { T 56800 56450 5 10 1 1 0 3 1 net=VCC33:1 } C 56500 53700 1 0 0 EMBEDDEDgeneric-power.sym [ P 56700 53700 56700 53900 1 0 0 { T 56750 53750 5 6 0 1 0 0 1 pinnumber=1 T 56750 53750 5 6 0 0 0 0 1 pinseq=1 T 56750 53750 5 6 0 1 0 0 1 pinlabel=1 T 56750 53750 5 6 0 1 0 0 1 pintype=pwr } L 56550 53900 56850 53900 3 0 0 0 -1 -1 T 56700 53950 8 10 0 1 0 3 1 net=Vcc:1 ] { T 56700 53950 5 10 1 1 0 3 1 net=VCC33:1 } C 50200 42500 1 180 0 EMBEDDEDgeneric_rgb.sym [ T 49250 41850 5 10 0 0 180 0 1 device=OVSRRGBCC3 T 49250 41950 5 10 0 0 180 0 1 description=RGB Common-Anode LED T 49250 42050 5 10 0 0 180 0 1 numslots=0 L 49600 41900 50000 41900 3 0 0 0 -1 -1 L 49600 41900 49800 42200 3 0 0 0 -1 -1 L 49800 42200 50000 41900 3 0 0 0 -1 -1 L 49600 42200 50000 42200 3 0 0 0 -1 -1 P 49800 42500 49800 42300 1 0 0 { T 49850 42395 5 8 0 1 270 6 1 pinnumber=1 T 49800 42245 9 8 0 1 270 0 1 pinlabel=RED T 50450 41600 5 8 0 0 90 0 1 pintype=pas T 50550 41900 5 8 0 0 90 0 1 pinseq=1 } L 49800 42300 49800 42200 3 0 0 0 -1 -1 L 49800 41900 49800 41800 3 0 0 0 -1 -1 L 50000 42000 50100 42100 3 0 0 0 -1 -1 L 50000 42100 50100 42200 3 0 0 0 -1 -1 L 50100 42200 50050 42175 3 0 0 0 -1 -1 L 50100 42200 50075 42150 3 0 0 0 -1 -1 L 50100 42100 50050 42075 3 0 0 0 -1 -1 L 50100 42100 50075 42050 3 0 0 0 -1 -1 T 48550 41550 8 10 0 1 0 0 1 refdes=D? L 48900 41900 49300 41900 3 0 0 0 -1 -1 L 48900 41900 49100 42200 3 0 0 0 -1 -1 L 49100 42200 49300 41900 3 0 0 0 -1 -1 L 48900 42200 49300 42200 3 0 0 0 -1 -1 P 49100 42500 49100 42300 1 0 0 { T 49150 42395 5 8 0 1 270 6 1 pinnumber=4 T 49100 42245 9 8 0 1 270 0 1 pinlabel=GREEN T 49750 41600 5 8 0 0 90 0 1 pintype=pas T 49850 41900 5 8 0 0 90 0 1 pinseq=4 } P 49100 41500 49100 41700 1 0 0 { T 49150 41605 5 8 0 1 270 0 1 pinnumber=2 T 49100 41755 9 8 0 1 270 6 1 pinlabel=ANODE T 49250 41400 5 8 0 0 90 8 1 pintype=pas T 49150 41400 5 8 0 0 90 8 1 pinseq=2 } L 49100 42300 49100 42200 3 0 0 0 -1 -1 L 49100 41900 49100 41700 3 0 0 0 -1 -1 L 49300 42000 49400 42100 3 0 0 0 -1 -1 L 49300 42100 49400 42200 3 0 0 0 -1 -1 L 49400 42200 49350 42175 3 0 0 0 -1 -1 L 49400 42200 49375 42150 3 0 0 0 -1 -1 L 49400 42100 49350 42075 3 0 0 0 -1 -1 L 49400 42100 49375 42050 3 0 0 0 -1 -1 L 48200 41900 48600 41900 3 0 0 0 -1 -1 L 48200 41900 48400 42200 3 0 0 0 -1 -1 L 48400 42200 48600 41900 3 0 0 0 -1 -1 L 48200 42200 48600 42200 3 0 0 0 -1 -1 P 48400 42500 48400 42300 1 0 0 { T 48450 42395 5 8 0 1 270 6 1 pinnumber=3 T 48400 42245 9 8 0 1 270 0 1 pinlabel=BLUE T 49050 41600 5 8 0 0 90 0 1 pintype=pas T 49150 41900 5 8 0 0 90 0 1 pinseq=3 } L 48400 42300 48400 42200 3 0 0 0 -1 -1 L 48400 41900 48400 41800 3 0 0 0 -1 -1 L 48600 42000 48700 42100 3 0 0 0 -1 -1 L 48600 42100 48700 42200 3 0 0 0 -1 -1 L 48700 42200 48650 42175 3 0 0 0 -1 -1 L 48700 42200 48675 42150 3 0 0 0 -1 -1 L 48700 42100 48650 42075 3 0 0 0 -1 -1 L 48700 42100 48675 42050 3 0 0 0 -1 -1 L 49800 41800 49100 41800 3 0 0 0 -1 -1 L 49100 41800 48400 41800 3 0 0 0 -1 -1 A 48300 42000 300 90 180 3 0 0 0 -1 -1 A 49900 42000 300 270 180 3 0 0 0 -1 -1 L 49900 41700 48300 41700 3 0 0 0 -1 -1 L 49900 42300 48300 42300 3 0 0 0 -1 -1 T 49700 42200 9 10 1 0 180 0 1 R T 49000 42200 9 10 1 0 180 0 1 G T 48300 42200 9 10 1 0 180 0 1 B ] { T 49250 41850 5 10 0 0 180 0 1 device=CLV1A-FKB T 48550 41550 5 10 1 1 0 0 1 refdes=D100 T 50200 42500 5 10 0 0 180 0 1 footprint=PLCC4 } C 50500 41600 1 0 0 EMBEDDEDgeneric-power.sym [ P 50700 41600 50700 41800 1 0 0 { T 50750 41650 5 6 0 1 0 0 1 pinnumber=1 T 50750 41650 5 6 0 0 0 0 1 pinseq=1 T 50750 41650 5 6 0 1 0 0 1 pinlabel=1 T 50750 41650 5 6 0 1 0 0 1 pintype=pwr } L 50550 41800 50850 41800 3 0 0 0 -1 -1 T 50700 41850 8 10 0 1 0 3 1 net=Vcc:1 ] { T 50700 41850 5 10 1 1 0 3 1 net=VCC33:1 } N 50700 41600 50700 41100 4 N 50700 41100 49100 41100 4 N 49100 41100 49100 41500 4 C 48500 42500 1 90 0 EMBEDDEDresistor-1.sym [ L 48300 43100 48500 43000 3 0 0 0 -1 -1 L 48500 43000 48300 42900 3 0 0 0 -1 -1 L 48300 42900 48500 42800 3 0 0 0 -1 -1 L 48500 42800 48300 42700 3 0 0 0 -1 -1 T 48100 42800 5 10 0 0 90 0 1 device=RESISTOR L 48300 43100 48500 43200 3 0 0 0 -1 -1 L 48500 43200 48400 43250 3 0 0 0 -1 -1 P 48400 43400 48400 43250 1 0 0 { T 48350 43300 5 8 0 1 90 0 1 pinnumber=2 T 48350 43300 5 8 0 0 90 0 1 pinseq=2 T 48350 43300 5 8 0 1 90 0 1 pinlabel=2 T 48350 43300 5 8 0 1 90 0 1 pintype=pas } P 48400 42500 48400 42652 1 0 0 { T 48350 42600 5 8 0 1 90 0 1 pinnumber=1 T 48350 42600 5 8 0 0 90 0 1 pinseq=1 T 48350 42600 5 8 0 1 90 0 1 pinlabel=1 T 48350 42600 5 8 0 1 90 0 1 pintype=pas } L 48300 42701 48400 42650 3 0 0 0 -1 -1 T 48200 42700 8 10 0 1 90 0 1 refdes=R? T 48500 42500 8 10 0 1 90 0 1 pins=2 T 48500 42500 8 10 0 1 90 0 1 class=DISCRETE ] { T 48100 42800 5 10 0 0 90 0 1 device=RESISTOR T 48200 42700 5 10 1 1 90 0 1 refdes=R105 T 48500 42500 5 10 0 1 0 0 1 footprint=0402 T 48700 42700 5 10 1 1 90 0 1 value=22 } C 49200 42500 1 90 0 EMBEDDEDresistor-1.sym [ L 49000 43100 49200 43000 3 0 0 0 -1 -1 L 49200 43000 49000 42900 3 0 0 0 -1 -1 L 49000 42900 49200 42800 3 0 0 0 -1 -1 L 49200 42800 49000 42700 3 0 0 0 -1 -1 T 48800 42800 5 10 0 0 90 0 1 device=RESISTOR L 49000 43100 49200 43200 3 0 0 0 -1 -1 L 49200 43200 49100 43250 3 0 0 0 -1 -1 P 49100 43400 49100 43250 1 0 0 { T 49050 43300 5 8 0 1 90 0 1 pinnumber=2 T 49050 43300 5 8 0 0 90 0 1 pinseq=2 T 49050 43300 5 8 0 1 90 0 1 pinlabel=2 T 49050 43300 5 8 0 1 90 0 1 pintype=pas } P 49100 42500 49100 42652 1 0 0 { T 49050 42600 5 8 0 1 90 0 1 pinnumber=1 T 49050 42600 5 8 0 0 90 0 1 pinseq=1 T 49050 42600 5 8 0 1 90 0 1 pinlabel=1 T 49050 42600 5 8 0 1 90 0 1 pintype=pas } L 49000 42701 49100 42650 3 0 0 0 -1 -1 T 48900 42700 8 10 0 1 90 0 1 refdes=R? T 49200 42500 8 10 0 1 90 0 1 pins=2 T 49200 42500 8 10 0 1 90 0 1 class=DISCRETE ] { T 48800 42800 5 10 0 2 90 0 1 device=RESISTOR T 48900 42700 5 10 1 1 90 0 1 refdes=R104 T 49200 42500 5 10 0 1 0 0 1 footprint=0402 T 49400 42700 5 10 1 1 90 0 1 value=22 } C 49900 42500 1 90 0 EMBEDDEDresistor-1.sym [ L 49700 43100 49900 43000 3 0 0 0 -1 -1 L 49900 43000 49700 42900 3 0 0 0 -1 -1 L 49700 42900 49900 42800 3 0 0 0 -1 -1 L 49900 42800 49700 42700 3 0 0 0 -1 -1 T 49500 42800 5 10 0 0 90 0 1 device=RESISTOR L 49700 43100 49900 43200 3 0 0 0 -1 -1 L 49900 43200 49800 43250 3 0 0 0 -1 -1 P 49800 43400 49800 43250 1 0 0 { T 49750 43300 5 8 0 1 90 0 1 pinnumber=2 T 49750 43300 5 8 0 0 90 0 1 pinseq=2 T 49750 43300 5 8 0 1 90 0 1 pinlabel=2 T 49750 43300 5 8 0 1 90 0 1 pintype=pas } P 49800 42500 49800 42652 1 0 0 { T 49750 42600 5 8 0 1 90 0 1 pinnumber=1 T 49750 42600 5 8 0 0 90 0 1 pinseq=1 T 49750 42600 5 8 0 1 90 0 1 pinlabel=1 T 49750 42600 5 8 0 1 90 0 1 pintype=pas } L 49700 42701 49800 42650 3 0 0 0 -1 -1 T 49600 42700 8 10 0 1 90 0 1 refdes=R? T 49900 42500 8 10 0 1 90 0 1 pins=2 T 49900 42500 8 10 0 1 90 0 1 class=DISCRETE ] { T 49500 42800 5 10 0 0 90 0 1 device=RESISTOR T 49600 42700 5 10 1 1 90 0 1 refdes=R103 T 49900 42500 5 10 0 1 0 0 1 footprint=0402 T 50100 42700 5 10 1 1 90 0 1 value=22 } N 49800 43400 49800 43500 4 N 49800 43500 50000 43500 4 N 49100 43400 49100 43900 4 N 49100 43900 50000 43900 4 N 48400 43400 48400 44300 4 N 48400 44300 50000 44300 4 C 57400 43900 1 90 0 EMBEDDEDswitch-spst-1.sym [ L 57200 44200 57400 44400 3 0 0 0 -1 -1 T 56700 44300 5 10 0 0 90 0 1 device=SPST P 57400 44400 57400 44700 1 0 1 { T 57350 44550 5 8 1 1 90 0 1 pinnumber=2 T 57350 44550 5 8 0 0 90 0 1 pinseq=2 T 57350 44550 5 8 0 1 90 0 1 pinlabel=2 T 57350 44550 5 8 0 1 90 0 1 pintype=pas } P 57400 44200 57400 43900 1 0 1 { T 57350 44000 5 8 1 1 90 0 1 pinnumber=1 T 57350 44000 5 8 0 0 90 0 1 pinseq=1 T 57350 44000 5 8 0 1 90 0 1 pinlabel=1 T 57350 44000 5 8 0 1 90 0 1 pintype=pas } T 57100 44200 8 10 0 1 90 0 1 refdes=S? ] { T 56700 44300 5 10 0 0 90 0 1 device=SPST T 57100 44200 5 10 1 1 90 0 1 refdes=S101 T 57400 43900 5 10 0 0 0 0 1 footprint=TACT_SKHUA } C 57300 43500 1 0 0 EMBEDDEDgnd-1.sym [ P 57400 43600 57400 43800 1 0 1 { T 57458 43661 5 4 0 1 0 0 1 pinnumber=1 T 57458 43661 5 4 0 0 0 0 1 pinseq=1 T 57458 43661 5 4 0 1 0 0 1 pinlabel=1 T 57458 43661 5 4 0 1 0 0 1 pintype=pwr } L 57300 43600 57500 43600 3 0 0 0 -1 -1 L 57355 43550 57445 43550 3 0 0 0 -1 -1 L 57380 43510 57420 43510 3 0 0 0 -1 -1 T 57600 43550 8 10 0 0 0 0 1 net=GND:1 ] { T 57100 43300 5 10 1 1 0 0 1 net=GND:1 } N 57400 43800 57400 43900 4